545 lines
22 KiB
C++
545 lines
22 KiB
C++
//===-- llvm/CodeGen/GlobalISel/CombinerHelper.h --------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===--------------------------------------------------------------------===//
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//
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/// This contains common combine transformations that may be used in a combine
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/// pass,or by the target elsewhere.
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/// Targets can pick individual opcode transformations from the helper or use
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/// tryCombine which invokes all transformations. All of the transformations
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/// return true if the MachineInstruction changed and false otherwise.
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//
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//===--------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_COMBINER_HELPER_H
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#define LLVM_CODEGEN_GLOBALISEL_COMBINER_HELPER_H
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/Support/Alignment.h"
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namespace llvm {
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class GISelChangeObserver;
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class MachineIRBuilder;
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class MachineInstrBuilder;
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class MachineRegisterInfo;
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class MachineInstr;
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class MachineOperand;
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class GISelKnownBits;
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class MachineDominatorTree;
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class LegalizerInfo;
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struct LegalityQuery;
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class TargetLowering;
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struct PreferredTuple {
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LLT Ty; // The result type of the extend.
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unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
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MachineInstr *MI;
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};
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struct IndexedLoadStoreMatchInfo {
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Register Addr;
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Register Base;
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Register Offset;
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bool IsPre;
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};
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struct PtrAddChain {
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int64_t Imm;
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Register Base;
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};
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struct RegisterImmPair {
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Register Reg;
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int64_t Imm;
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};
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struct ShiftOfShiftedLogic {
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MachineInstr *Logic;
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MachineInstr *Shift2;
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Register LogicNonShiftReg;
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uint64_t ValSum;
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};
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using OperandBuildSteps =
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SmallVector<std::function<void(MachineInstrBuilder &)>, 4>;
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struct InstructionBuildSteps {
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unsigned Opcode = 0; /// The opcode for the produced instruction.
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OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
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InstructionBuildSteps() = default;
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InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
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: Opcode(Opcode), OperandFns(OperandFns) {}
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};
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struct InstructionStepsMatchInfo {
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/// Describes instructions to be built during a combine.
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SmallVector<InstructionBuildSteps, 2> InstrsToBuild;
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InstructionStepsMatchInfo() = default;
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InstructionStepsMatchInfo(
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std::initializer_list<InstructionBuildSteps> InstrsToBuild)
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: InstrsToBuild(InstrsToBuild) {}
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};
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class CombinerHelper {
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protected:
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MachineIRBuilder &Builder;
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MachineRegisterInfo &MRI;
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GISelChangeObserver &Observer;
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GISelKnownBits *KB;
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MachineDominatorTree *MDT;
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const LegalizerInfo *LI;
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public:
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CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B,
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GISelKnownBits *KB = nullptr,
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MachineDominatorTree *MDT = nullptr,
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const LegalizerInfo *LI = nullptr);
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GISelKnownBits *getKnownBits() const {
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return KB;
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}
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const TargetLowering &getTargetLowering() const;
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/// \return true if the combine is running prior to legalization, or if \p
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/// Query is legal on the target.
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bool isLegalOrBeforeLegalizer(const LegalityQuery &Query) const;
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/// MachineRegisterInfo::replaceRegWith() and inform the observer of the changes
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void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
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/// Replace a single register operand with a new register and inform the
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/// observer of the changes.
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void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp,
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Register ToReg) const;
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/// If \p MI is COPY, try to combine it.
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/// Returns true if MI changed.
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bool tryCombineCopy(MachineInstr &MI);
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bool matchCombineCopy(MachineInstr &MI);
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void applyCombineCopy(MachineInstr &MI);
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/// Returns true if \p DefMI precedes \p UseMI or they are the same
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/// instruction. Both must be in the same basic block.
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bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
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/// Returns true if \p DefMI dominates \p UseMI. By definition an
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/// instruction dominates itself.
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///
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/// If we haven't been provided with a MachineDominatorTree during
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/// construction, this function returns a conservative result that tracks just
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/// a single basic block.
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bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
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/// If \p MI is extend that consumes the result of a load, try to combine it.
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/// Returns true if MI changed.
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bool tryCombineExtendingLoads(MachineInstr &MI);
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bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
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void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
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/// Combine \p MI into a pre-indexed or post-indexed load/store operation if
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/// legal and the surrounding code makes it useful.
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bool tryCombineIndexedLoadStore(MachineInstr &MI);
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bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
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void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
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bool matchSextTruncSextLoad(MachineInstr &MI);
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bool applySextTruncSextLoad(MachineInstr &MI);
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/// Match sext_inreg(load p), imm -> sextload p
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bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
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bool applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
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/// If a brcond's true block is not the fallthrough, make it so by inverting
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/// the condition and swapping operands.
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bool matchOptBrCondByInvertingCond(MachineInstr &MI);
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void applyOptBrCondByInvertingCond(MachineInstr &MI);
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/// If \p MI is G_CONCAT_VECTORS, try to combine it.
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/// Returns true if MI changed.
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/// Right now, we support:
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/// - concat_vector(undef, undef) => undef
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/// - concat_vector(build_vector(A, B), build_vector(C, D)) =>
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/// build_vector(A, B, C, D)
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///
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/// \pre MI.getOpcode() == G_CONCAT_VECTORS.
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bool tryCombineConcatVectors(MachineInstr &MI);
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/// Check if the G_CONCAT_VECTORS \p MI is undef or if it
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/// can be flattened into a build_vector.
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/// In the first case \p IsUndef will be true.
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/// In the second case \p Ops will contain the operands needed
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/// to produce the flattened build_vector.
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///
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/// \pre MI.getOpcode() == G_CONCAT_VECTORS.
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bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
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SmallVectorImpl<Register> &Ops);
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/// Replace \p MI with a flattened build_vector with \p Ops or an
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/// implicit_def if IsUndef is true.
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void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
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const ArrayRef<Register> Ops);
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/// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
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/// Returns true if MI changed.
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///
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/// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
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bool tryCombineShuffleVector(MachineInstr &MI);
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/// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
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/// concat_vectors.
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/// \p Ops will contain the operands needed to produce the flattened
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/// concat_vectors.
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///
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/// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
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bool matchCombineShuffleVector(MachineInstr &MI,
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SmallVectorImpl<Register> &Ops);
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/// Replace \p MI with a concat_vectors with \p Ops.
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void applyCombineShuffleVector(MachineInstr &MI,
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const ArrayRef<Register> Ops);
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/// Optimize memcpy intrinsics et al, e.g. constant len calls.
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/// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
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///
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/// For example (pre-indexed):
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///
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/// $addr = G_PTR_ADD $base, $offset
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/// [...]
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/// $val = G_LOAD $addr
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/// [...]
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/// $whatever = COPY $addr
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///
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/// -->
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///
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/// $val, $addr = G_INDEXED_LOAD $base, $offset, 1 (IsPre)
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/// [...]
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/// $whatever = COPY $addr
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///
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/// or (post-indexed):
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///
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/// G_STORE $val, $base
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/// [...]
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/// $addr = G_PTR_ADD $base, $offset
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/// [...]
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/// $whatever = COPY $addr
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///
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/// -->
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///
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/// $addr = G_INDEXED_STORE $val, $base, $offset
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/// [...]
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/// $whatever = COPY $addr
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bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
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bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
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bool applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
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/// Fold (shift (shift base, x), y) -> (shift base (x+y))
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bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
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bool applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
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/// If we have a shift-by-constant of a bitwise logic op that itself has a
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/// shift-by-constant operand with identical opcode, we may be able to convert
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/// that into 2 independent shifts followed by the logic op.
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bool matchShiftOfShiftedLogic(MachineInstr &MI,
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ShiftOfShiftedLogic &MatchInfo);
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bool applyShiftOfShiftedLogic(MachineInstr &MI,
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ShiftOfShiftedLogic &MatchInfo);
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/// Transform a multiply by a power-of-2 value to a left shift.
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bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
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bool applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
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// Transform a G_SHL with an extended source into a narrower shift if
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// possible.
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bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData);
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bool applyCombineShlOfExtend(MachineInstr &MI,
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const RegisterImmPair &MatchData);
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/// Reduce a shift by a constant to an unmerge and a shift on a half sized
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/// type. This will not produce a shift smaller than \p TargetShiftSize.
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bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
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unsigned &ShiftVal);
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bool applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
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bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
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/// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
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bool
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matchCombineUnmergeMergeToPlainValues(MachineInstr &MI,
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SmallVectorImpl<Register> &Operands);
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bool
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applyCombineUnmergeMergeToPlainValues(MachineInstr &MI,
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SmallVectorImpl<Register> &Operands);
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/// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
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bool matchCombineUnmergeConstant(MachineInstr &MI,
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SmallVectorImpl<APInt> &Csts);
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bool applyCombineUnmergeConstant(MachineInstr &MI,
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SmallVectorImpl<APInt> &Csts);
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/// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
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bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI);
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bool applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI);
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/// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
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bool matchCombineUnmergeZExtToZExt(MachineInstr &MI);
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bool applyCombineUnmergeZExtToZExt(MachineInstr &MI);
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/// Transform fp_instr(cst) to constant result of the fp operation.
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bool matchCombineConstantFoldFpUnary(MachineInstr &MI,
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Optional<APFloat> &Cst);
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bool applyCombineConstantFoldFpUnary(MachineInstr &MI,
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Optional<APFloat> &Cst);
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/// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
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bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg);
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bool applyCombineI2PToP2I(MachineInstr &MI, Register &Reg);
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/// Transform PtrToInt(IntToPtr(x)) to x.
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bool matchCombineP2IToI2P(MachineInstr &MI, Register &Reg);
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bool applyCombineP2IToI2P(MachineInstr &MI, Register &Reg);
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/// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
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/// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
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bool matchCombineAddP2IToPtrAdd(MachineInstr &MI,
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std::pair<Register, bool> &PtrRegAndCommute);
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bool applyCombineAddP2IToPtrAdd(MachineInstr &MI,
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std::pair<Register, bool> &PtrRegAndCommute);
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// Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
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bool matchCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
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bool applyCombineConstPtrAddToI2P(MachineInstr &MI, int64_t &NewCst);
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/// Transform anyext(trunc(x)) to x.
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bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg);
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bool applyCombineAnyExtTrunc(MachineInstr &MI, Register &Reg);
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/// Transform [asz]ext([asz]ext(x)) to [asz]ext x.
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bool matchCombineExtOfExt(MachineInstr &MI,
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std::tuple<Register, unsigned> &MatchInfo);
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bool applyCombineExtOfExt(MachineInstr &MI,
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std::tuple<Register, unsigned> &MatchInfo);
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/// Transform fneg(fneg(x)) to x.
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bool matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg);
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/// Match fabs(fabs(x)) to fabs(x).
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bool matchCombineFAbsOfFAbs(MachineInstr &MI, Register &Src);
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bool applyCombineFAbsOfFAbs(MachineInstr &MI, Register &Src);
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/// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
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bool matchCombineTruncOfExt(MachineInstr &MI,
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std::pair<Register, unsigned> &MatchInfo);
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bool applyCombineTruncOfExt(MachineInstr &MI,
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std::pair<Register, unsigned> &MatchInfo);
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/// Transform trunc (shl x, K) to shl (trunc x),
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/// K => K < VT.getScalarSizeInBits().
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bool matchCombineTruncOfShl(MachineInstr &MI,
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std::pair<Register, Register> &MatchInfo);
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bool applyCombineTruncOfShl(MachineInstr &MI,
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std::pair<Register, Register> &MatchInfo);
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/// Transform G_MUL(x, -1) to G_SUB(0, x)
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bool applyCombineMulByNegativeOne(MachineInstr &MI);
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/// Return true if any explicit use operand on \p MI is defined by a
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/// G_IMPLICIT_DEF.
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bool matchAnyExplicitUseIsUndef(MachineInstr &MI);
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/// Return true if all register explicit use operands on \p MI are defined by
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/// a G_IMPLICIT_DEF.
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bool matchAllExplicitUsesAreUndef(MachineInstr &MI);
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/// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
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bool matchUndefShuffleVectorMask(MachineInstr &MI);
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/// Return true if a G_STORE instruction \p MI is storing an undef value.
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bool matchUndefStore(MachineInstr &MI);
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/// Return true if a G_SELECT instruction \p MI has an undef comparison.
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bool matchUndefSelectCmp(MachineInstr &MI);
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/// Return true if a G_SELECT instruction \p MI has a constant comparison. If
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/// true, \p OpIdx will store the operand index of the known selected value.
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bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx);
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/// Replace an instruction with a G_FCONSTANT with value \p C.
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bool replaceInstWithFConstant(MachineInstr &MI, double C);
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/// Replace an instruction with a G_CONSTANT with value \p C.
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bool replaceInstWithConstant(MachineInstr &MI, int64_t C);
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/// Replace an instruction with a G_IMPLICIT_DEF.
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bool replaceInstWithUndef(MachineInstr &MI);
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/// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
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bool replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
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/// Delete \p MI and replace all of its uses with \p Replacement.
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bool replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement);
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/// Return true if \p MOP1 and \p MOP2 are register operands are defined by
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/// equivalent instructions.
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bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
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/// Return true if \p MOP is defined by a G_CONSTANT with a value equal to
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/// \p C.
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bool matchConstantOp(const MachineOperand &MOP, int64_t C);
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/// Optimize (cond ? x : x) -> x
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bool matchSelectSameVal(MachineInstr &MI);
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/// Optimize (x op x) -> x
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bool matchBinOpSameVal(MachineInstr &MI);
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/// Check if operand \p OpIdx is zero.
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bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx);
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/// Check if operand \p OpIdx is undef.
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bool matchOperandIsUndef(MachineInstr &MI, unsigned OpIdx);
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/// Check if operand \p OpIdx is known to be a power of 2.
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bool matchOperandIsKnownToBeAPowerOfTwo(MachineInstr &MI, unsigned OpIdx);
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/// Erase \p MI
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bool eraseInst(MachineInstr &MI);
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/// Return true if MI is a G_ADD which can be simplified to a G_SUB.
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bool matchSimplifyAddToSub(MachineInstr &MI,
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std::tuple<Register, Register> &MatchInfo);
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bool applySimplifyAddToSub(MachineInstr &MI,
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std::tuple<Register, Register> &MatchInfo);
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/// Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
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bool
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matchHoistLogicOpWithSameOpcodeHands(MachineInstr &MI,
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InstructionStepsMatchInfo &MatchInfo);
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/// Replace \p MI with a series of instructions described in \p MatchInfo.
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bool applyBuildInstructionSteps(MachineInstr &MI,
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InstructionStepsMatchInfo &MatchInfo);
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/// Match ashr (shl x, C), C -> sext_inreg (C)
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bool matchAshrShlToSextInreg(MachineInstr &MI,
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std::tuple<Register, int64_t> &MatchInfo);
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bool applyAshShlToSextInreg(MachineInstr &MI,
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std::tuple<Register, int64_t> &MatchInfo);
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/// \return true if \p MI is a G_AND instruction whose operands are x and y
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/// where x & y == x or x & y == y. (E.g., one of operands is all-ones value.)
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///
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/// \param [in] MI - The G_AND instruction.
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/// \param [out] Replacement - A register the G_AND should be replaced with on
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/// success.
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bool matchRedundantAnd(MachineInstr &MI, Register &Replacement);
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/// \return true if \p MI is a G_OR instruction whose operands are x and y
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/// where x | y == x or x | y == y. (E.g., one of operands is all-zeros
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/// value.)
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///
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/// \param [in] MI - The G_OR instruction.
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/// \param [out] Replacement - A register the G_OR should be replaced with on
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/// success.
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bool matchRedundantOr(MachineInstr &MI, Register &Replacement);
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/// \return true if \p MI is a G_SEXT_INREG that can be erased.
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bool matchRedundantSExtInReg(MachineInstr &MI);
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/// Combine inverting a result of a compare into the opposite cond code.
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bool matchNotCmp(MachineInstr &MI, SmallVectorImpl<Register> &RegsToNegate);
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bool applyNotCmp(MachineInstr &MI, SmallVectorImpl<Register> &RegsToNegate);
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/// Fold (xor (and x, y), y) -> (and (not x), y)
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///{
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bool matchXorOfAndWithSameReg(MachineInstr &MI,
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std::pair<Register, Register> &MatchInfo);
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bool applyXorOfAndWithSameReg(MachineInstr &MI,
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std::pair<Register, Register> &MatchInfo);
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///}
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/// Combine G_PTR_ADD with nullptr to G_INTTOPTR
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bool matchPtrAddZero(MachineInstr &MI);
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bool applyPtrAddZero(MachineInstr &MI);
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/// Combine G_UREM x, (known power of 2) to an add and bitmasking.
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bool applySimplifyURemByPow2(MachineInstr &MI);
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bool matchCombineInsertVecElts(MachineInstr &MI,
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SmallVectorImpl<Register> &MatchInfo);
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|
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bool applyCombineInsertVecElts(MachineInstr &MI,
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|
SmallVectorImpl<Register> &MatchInfo);
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|
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/// Match expression trees of the form
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///
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/// \code
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/// sN *a = ...
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/// sM val = a[0] | (a[1] << N) | (a[2] << 2N) | (a[3] << 3N) ...
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/// \endcode
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///
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/// And check if the tree can be replaced with a M-bit load + possibly a
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/// bswap.
|
|
bool matchLoadOrCombine(MachineInstr &MI,
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|
std::function<void(MachineIRBuilder &)> &MatchInfo);
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bool applyLoadOrCombine(MachineInstr &MI,
|
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std::function<void(MachineIRBuilder &)> &MatchInfo);
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|
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/// Try to transform \p MI by using all of the above
|
|
/// combine functions. Returns true if changed.
|
|
bool tryCombine(MachineInstr &MI);
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|
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|
private:
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// Memcpy family optimization helpers.
|
|
bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
|
|
unsigned KnownLen, Align DstAlign, Align SrcAlign,
|
|
bool IsVolatile);
|
|
bool optimizeMemmove(MachineInstr &MI, Register Dst, Register Src,
|
|
unsigned KnownLen, Align DstAlign, Align SrcAlign,
|
|
bool IsVolatile);
|
|
bool optimizeMemset(MachineInstr &MI, Register Dst, Register Val,
|
|
unsigned KnownLen, Align DstAlign, bool IsVolatile);
|
|
|
|
/// Given a non-indexed load or store instruction \p MI, find an offset that
|
|
/// can be usefully and legally folded into it as a post-indexing operation.
|
|
///
|
|
/// \returns true if a candidate is found.
|
|
bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
|
|
Register &Offset);
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|
|
|
/// Given a non-indexed load or store instruction \p MI, find an offset that
|
|
/// can be usefully and legally folded into it as a pre-indexing operation.
|
|
///
|
|
/// \returns true if a candidate is found.
|
|
bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
|
|
Register &Offset);
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|
|
|
/// Helper function for matchLoadOrCombine. Searches for Registers
|
|
/// which may have been produced by a load instruction + some arithmetic.
|
|
///
|
|
/// \param [in] Root - The search root.
|
|
///
|
|
/// \returns The Registers found during the search.
|
|
Optional<SmallVector<Register, 8>>
|
|
findCandidatesForLoadOrCombine(const MachineInstr *Root) const;
|
|
|
|
/// Helper function for matchLoadOrCombine.
|
|
///
|
|
/// Checks if every register in \p RegsToVisit is defined by a load
|
|
/// instruction + some arithmetic.
|
|
///
|
|
/// \param [out] MemOffset2Idx - Maps the byte positions each load ends up
|
|
/// at to the index of the load.
|
|
/// \param [in] MemSizeInBits - The number of bits each load should produce.
|
|
///
|
|
/// \returns The lowest-index load found and the lowest index on success.
|
|
Optional<std::pair<MachineInstr *, int64_t>> findLoadOffsetsForLoadOrCombine(
|
|
SmallDenseMap<int64_t, int64_t, 8> &MemOffset2Idx,
|
|
const SmallVector<Register, 8> &RegsToVisit,
|
|
const unsigned MemSizeInBits);
|
|
};
|
|
} // namespace llvm
|
|
|
|
#endif
|