464 lines
19 KiB
C++
464 lines
19 KiB
C++
//===- llvm/CodeGen/GlobalISel/CallLowering.h - Call lowering ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file describes how to lower LLVM calls to machine code calls.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
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#define LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetCallingConv.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MachineValueType.h"
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#include <cstdint>
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#include <functional>
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namespace llvm {
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class CallBase;
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class DataLayout;
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class Function;
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class FunctionLoweringInfo;
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class MachineIRBuilder;
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struct MachinePointerInfo;
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class MachineRegisterInfo;
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class TargetLowering;
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class Value;
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class CallLowering {
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const TargetLowering *TLI;
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virtual void anchor();
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public:
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struct BaseArgInfo {
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Type *Ty;
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SmallVector<ISD::ArgFlagsTy, 4> Flags;
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bool IsFixed;
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BaseArgInfo(Type *Ty,
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ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
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bool IsFixed = true)
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: Ty(Ty), Flags(Flags.begin(), Flags.end()), IsFixed(IsFixed) {}
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BaseArgInfo() : Ty(nullptr), IsFixed(false) {}
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};
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struct ArgInfo : public BaseArgInfo {
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SmallVector<Register, 4> Regs;
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// If the argument had to be split into multiple parts according to the
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// target calling convention, then this contains the original vregs
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// if the argument was an incoming arg.
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SmallVector<Register, 2> OrigRegs;
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ArgInfo(ArrayRef<Register> Regs, Type *Ty,
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ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
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bool IsFixed = true)
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: BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()) {
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if (!Regs.empty() && Flags.empty())
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this->Flags.push_back(ISD::ArgFlagsTy());
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// FIXME: We should have just one way of saying "no register".
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assert(((Ty->isVoidTy() || Ty->isEmptyTy()) ==
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(Regs.empty() || Regs[0] == 0)) &&
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"only void types should have no register");
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}
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ArgInfo() : BaseArgInfo() {}
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};
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struct CallLoweringInfo {
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/// Calling convention to be used for the call.
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CallingConv::ID CallConv = CallingConv::C;
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/// Destination of the call. It should be either a register, globaladdress,
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/// or externalsymbol.
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MachineOperand Callee = MachineOperand::CreateImm(0);
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/// Descriptor for the return type of the function.
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ArgInfo OrigRet;
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/// List of descriptors of the arguments passed to the function.
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SmallVector<ArgInfo, 8> OrigArgs;
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/// Valid if the call has a swifterror inout parameter, and contains the
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/// vreg that the swifterror should be copied into after the call.
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Register SwiftErrorVReg;
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MDNode *KnownCallees = nullptr;
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/// True if the call must be tail call optimized.
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bool IsMustTailCall = false;
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/// True if the call passes all target-independent checks for tail call
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/// optimization.
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bool IsTailCall = false;
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/// True if the call was lowered as a tail call. This is consumed by the
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/// legalizer. This allows the legalizer to lower libcalls as tail calls.
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bool LoweredTailCall = false;
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/// True if the call is to a vararg function.
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bool IsVarArg = false;
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/// True if the function's return value can be lowered to registers.
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bool CanLowerReturn = true;
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/// VReg to hold the hidden sret parameter.
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Register DemoteRegister;
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/// The stack index for sret demotion.
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int DemoteStackIndex;
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};
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/// Argument handling is mostly uniform between the four places that
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/// make these decisions: function formal arguments, call
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/// instruction args, call instruction returns and function
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/// returns. However, once a decision has been made on where an
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/// argument should go, exactly what happens can vary slightly. This
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/// class abstracts the differences.
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struct ValueHandler {
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ValueHandler(bool IsIncoming, MachineIRBuilder &MIRBuilder,
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MachineRegisterInfo &MRI, CCAssignFn *AssignFn)
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: MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn),
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IsIncomingArgumentHandler(IsIncoming) {}
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virtual ~ValueHandler() = default;
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/// Returns true if the handler is dealing with incoming arguments,
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/// i.e. those that move values from some physical location to vregs.
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bool isIncomingArgumentHandler() const {
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return IsIncomingArgumentHandler;
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}
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/// Materialize a VReg containing the address of the specified
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/// stack-based object. This is either based on a FrameIndex or
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/// direct SP manipulation, depending on the context. \p MPO
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/// should be initialized to an appropriate description of the
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/// address created.
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virtual Register getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO) = 0;
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/// The specified value has been assigned to a physical register,
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/// handle the appropriate COPY (either to or from) and mark any
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/// relevant uses/defines as needed.
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virtual void assignValueToReg(Register ValVReg, Register PhysReg,
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CCValAssign &VA) = 0;
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/// The specified value has been assigned to a stack
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/// location. Load or store it there, with appropriate extension
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/// if necessary.
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virtual void assignValueToAddress(Register ValVReg, Register Addr,
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uint64_t Size, MachinePointerInfo &MPO,
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CCValAssign &VA) = 0;
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/// An overload which takes an ArgInfo if additional information about
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/// the arg is needed.
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virtual void assignValueToAddress(const ArgInfo &Arg, Register Addr,
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uint64_t Size, MachinePointerInfo &MPO,
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CCValAssign &VA) {
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assert(Arg.Regs.size() == 1);
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assignValueToAddress(Arg.Regs[0], Addr, Size, MPO, VA);
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}
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/// Handle custom values, which may be passed into one or more of \p VAs.
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/// \return The number of \p VAs that have been assigned after the first
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/// one, and which should therefore be skipped from further
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/// processing.
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virtual unsigned assignCustomValue(const ArgInfo &Arg,
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ArrayRef<CCValAssign> VAs) {
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// This is not a pure virtual method because not all targets need to worry
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// about custom values.
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llvm_unreachable("Custom values not supported");
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}
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/// Extend a register to the location type given in VA, capped at extending
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/// to at most MaxSize bits. If MaxSizeBits is 0 then no maximum is set.
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Register extendRegister(Register ValReg, CCValAssign &VA,
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unsigned MaxSizeBits = 0);
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virtual bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo, const ArgInfo &Info,
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ISD::ArgFlagsTy Flags, CCState &State) {
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return AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
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}
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MachineIRBuilder &MIRBuilder;
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MachineRegisterInfo &MRI;
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CCAssignFn *AssignFn;
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private:
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bool IsIncomingArgumentHandler;
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virtual void anchor();
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};
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struct IncomingValueHandler : public ValueHandler {
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IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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CCAssignFn *AssignFn)
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: ValueHandler(true, MIRBuilder, MRI, AssignFn) {}
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};
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struct OutgoingValueHandler : public ValueHandler {
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OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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CCAssignFn *AssignFn)
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: ValueHandler(false, MIRBuilder, MRI, AssignFn) {}
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};
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protected:
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/// Getter for generic TargetLowering class.
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const TargetLowering *getTLI() const {
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return TLI;
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}
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/// Getter for target specific TargetLowering class.
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template <class XXXTargetLowering>
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const XXXTargetLowering *getTLI() const {
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return static_cast<const XXXTargetLowering *>(TLI);
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}
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/// \returns Flags corresponding to the attributes on the \p ArgIdx-th
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/// parameter of \p Call.
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ISD::ArgFlagsTy getAttributesForArgIdx(const CallBase &Call,
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unsigned ArgIdx) const;
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/// Adds flags to \p Flags based off of the attributes in \p Attrs.
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/// \p OpIdx is the index in \p Attrs to add flags from.
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void addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags,
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const AttributeList &Attrs,
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unsigned OpIdx) const;
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template <typename FuncInfoTy>
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void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL,
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const FuncInfoTy &FuncInfo) const;
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/// Generate instructions for packing \p SrcRegs into one big register
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/// corresponding to the aggregate type \p PackedTy.
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///
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/// \param SrcRegs should contain one virtual register for each base type in
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/// \p PackedTy, as returned by computeValueLLTs.
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///
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/// \return The packed register.
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Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
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MachineIRBuilder &MIRBuilder) const;
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/// Generate instructions for unpacking \p SrcReg into the \p DstRegs
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/// corresponding to the aggregate type \p PackedTy.
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///
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/// \param DstRegs should contain one virtual register for each base type in
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/// \p PackedTy, as returned by computeValueLLTs.
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void unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg, Type *PackedTy,
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MachineIRBuilder &MIRBuilder) const;
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/// Invoke Handler::assignArg on each of the given \p Args and then use
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/// \p Handler to move them to the assigned locations.
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///
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/// \return True if everything has succeeded, false otherwise.
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bool handleAssignments(MachineIRBuilder &MIRBuilder,
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SmallVectorImpl<ArgInfo> &Args,
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ValueHandler &Handler) const;
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bool handleAssignments(CCState &CCState,
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SmallVectorImpl<CCValAssign> &ArgLocs,
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MachineIRBuilder &MIRBuilder,
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SmallVectorImpl<ArgInfo> &Args,
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ValueHandler &Handler) const;
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/// Analyze passed or returned values from a call, supplied in \p ArgInfo,
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/// incorporating info about the passed values into \p CCState.
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///
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/// Used to check if arguments are suitable for tail call lowering.
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bool analyzeArgInfo(CCState &CCState, SmallVectorImpl<ArgInfo> &Args,
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CCAssignFn &AssignFnFixed,
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CCAssignFn &AssignFnVarArg) const;
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/// Check whether parameters to a call that are passed in callee saved
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/// registers are the same as from the calling function. This needs to be
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/// checked for tail call eligibility.
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bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
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const uint32_t *CallerPreservedMask,
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const SmallVectorImpl<CCValAssign> &ArgLocs,
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const SmallVectorImpl<ArgInfo> &OutVals) const;
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/// \returns True if the calling convention for a callee and its caller pass
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/// results in the same way. Typically used for tail call eligibility checks.
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///
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/// \p Info is the CallLoweringInfo for the call.
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/// \p MF is the MachineFunction for the caller.
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/// \p InArgs contains the results of the call.
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/// \p CalleeAssignFnFixed is the CCAssignFn to be used for the callee for
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/// fixed arguments.
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/// \p CalleeAssignFnVarArg is similar, but for varargs.
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/// \p CallerAssignFnFixed is the CCAssignFn to be used for the caller for
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/// fixed arguments.
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/// \p CallerAssignFnVarArg is similar, but for varargs.
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bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF,
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SmallVectorImpl<ArgInfo> &InArgs,
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CCAssignFn &CalleeAssignFnFixed,
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CCAssignFn &CalleeAssignFnVarArg,
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CCAssignFn &CallerAssignFnFixed,
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CCAssignFn &CallerAssignFnVarArg) const;
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public:
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CallLowering(const TargetLowering *TLI) : TLI(TLI) {}
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virtual ~CallLowering() = default;
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/// \return true if the target is capable of handling swifterror values that
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/// have been promoted to a specified register. The extended versions of
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/// lowerReturn and lowerCall should be implemented.
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virtual bool supportSwiftError() const {
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return false;
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}
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/// Load the returned value from the stack into virtual registers in \p VRegs.
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/// It uses the frame index \p FI and the start offset from \p DemoteReg.
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/// The loaded data size will be determined from \p RetTy.
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void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy,
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ArrayRef<Register> VRegs, Register DemoteReg,
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int FI) const;
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/// Store the return value given by \p VRegs into stack starting at the offset
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/// specified in \p DemoteReg.
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void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy,
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ArrayRef<Register> VRegs, Register DemoteReg) const;
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/// Insert the hidden sret ArgInfo to the beginning of \p SplitArgs.
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/// This function should be called from the target specific
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/// lowerFormalArguments when \p F requires the sret demotion.
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void insertSRetIncomingArgument(const Function &F,
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SmallVectorImpl<ArgInfo> &SplitArgs,
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Register &DemoteReg, MachineRegisterInfo &MRI,
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const DataLayout &DL) const;
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/// For the call-base described by \p CB, insert the hidden sret ArgInfo to
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/// the OrigArgs field of \p Info.
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void insertSRetOutgoingArgument(MachineIRBuilder &MIRBuilder,
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const CallBase &CB,
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CallLoweringInfo &Info) const;
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/// \return True if the return type described by \p Outs can be returned
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/// without performing sret demotion.
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bool checkReturn(CCState &CCInfo, SmallVectorImpl<BaseArgInfo> &Outs,
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CCAssignFn *Fn) const;
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/// Get the type and the ArgFlags for the split components of \p RetTy as
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/// returned by \c ComputeValueVTs.
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void getReturnInfo(CallingConv::ID CallConv, Type *RetTy, AttributeList Attrs,
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SmallVectorImpl<BaseArgInfo> &Outs,
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const DataLayout &DL) const;
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/// Toplevel function to check the return type based on the target calling
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/// convention. \return True if the return value of \p MF can be returned
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/// without performing sret demotion.
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bool checkReturnTypeForCallConv(MachineFunction &MF) const;
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/// This hook must be implemented to check whether the return values
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/// described by \p Outs can fit into the return registers. If false
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/// is returned, an sret-demotion is performed.
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virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
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SmallVectorImpl<BaseArgInfo> &Outs,
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bool IsVarArg) const {
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return true;
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}
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/// This hook must be implemented to lower outgoing return values, described
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/// by \p Val, into the specified virtual registers \p VRegs.
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/// This hook is used by GlobalISel.
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///
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/// \p FLI is required for sret demotion.
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///
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/// \p SwiftErrorVReg is non-zero if the function has a swifterror parameter
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/// that needs to be implicitly returned.
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///
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/// \return True if the lowering succeeds, false otherwise.
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virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
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ArrayRef<Register> VRegs, FunctionLoweringInfo &FLI,
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Register SwiftErrorVReg) const {
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if (!supportSwiftError()) {
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assert(SwiftErrorVReg == 0 && "attempt to use unsupported swifterror");
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return lowerReturn(MIRBuilder, Val, VRegs, FLI);
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}
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return false;
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}
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/// This hook behaves as the extended lowerReturn function, but for targets
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/// that do not support swifterror value promotion.
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virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
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ArrayRef<Register> VRegs,
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FunctionLoweringInfo &FLI) const {
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return false;
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}
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virtual bool fallBackToDAGISel(const Function &F) const { return false; }
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/// This hook must be implemented to lower the incoming (formal)
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/// arguments, described by \p VRegs, for GlobalISel. Each argument
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/// must end up in the related virtual registers described by \p VRegs.
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/// In other words, the first argument should end up in \c VRegs[0],
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/// the second in \c VRegs[1], and so on. For each argument, there will be one
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/// register for each non-aggregate type, as returned by \c computeValueLLTs.
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/// \p MIRBuilder is set to the proper insertion for the argument
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/// lowering. \p FLI is required for sret demotion.
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///
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/// \return True if the lowering succeeded, false otherwise.
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virtual bool lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs,
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FunctionLoweringInfo &FLI) const {
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return false;
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}
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/// This hook must be implemented to lower the given call instruction,
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/// including argument and return value marshalling.
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///
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///
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/// \return true if the lowering succeeded, false otherwise.
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virtual bool lowerCall(MachineIRBuilder &MIRBuilder,
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CallLoweringInfo &Info) const {
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return false;
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}
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/// Lower the given call instruction, including argument and return value
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/// marshalling.
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///
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/// \p CI is the call/invoke instruction.
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///
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/// \p ResRegs are the registers where the call's return value should be
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/// stored (or 0 if there is no return value). There will be one register for
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/// each non-aggregate type, as returned by \c computeValueLLTs.
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///
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/// \p ArgRegs is a list of lists of virtual registers containing each
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/// argument that needs to be passed (argument \c i should be placed in \c
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/// ArgRegs[i]). For each argument, there will be one register for each
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/// non-aggregate type, as returned by \c computeValueLLTs.
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///
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/// \p SwiftErrorVReg is non-zero if the call has a swifterror inout
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/// parameter, and contains the vreg that the swifterror should be copied into
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/// after the call.
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///
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/// \p GetCalleeReg is a callback to materialize a register for the callee if
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/// the target determines it cannot jump to the destination based purely on \p
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/// CI. This might be because \p CI is indirect, or because of the limited
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/// range of an immediate jump.
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///
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/// \return true if the lowering succeeded, false otherwise.
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bool lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &Call,
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ArrayRef<Register> ResRegs,
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ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
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std::function<unsigned()> GetCalleeReg) const;
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
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