397 lines
16 KiB
C++
397 lines
16 KiB
C++
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//===-- TargetTest.cpp -----------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "Target.h"
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#include <cassert>
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#include <memory>
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "gmock/gmock.h"
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#include "gtest/gtest.h"
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#include "llvm/MC/MCInstPrinter.h"
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namespace llvm {
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bool operator==(const MCOperand &a, const MCOperand &b) {
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if (a.isImm() && b.isImm())
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return a.getImm() == b.getImm();
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if (a.isReg() && b.isReg())
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return a.getReg() == b.getReg();
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return false;
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}
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bool operator==(const MCInst &a, const MCInst &b) {
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if (a.getOpcode() != b.getOpcode())
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return false;
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if (a.getNumOperands() != b.getNumOperands())
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return false;
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for (unsigned I = 0; I < a.getNumOperands(); ++I) {
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if (!(a.getOperand(I) == b.getOperand(I)))
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return false;
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}
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return true;
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}
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} // namespace llvm
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namespace llvm {
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namespace exegesis {
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void InitializeX86ExegesisTarget();
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namespace {
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using testing::AllOf;
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using testing::ElementsAre;
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using testing::ElementsAreArray;
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using testing::Eq;
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using testing::Gt;
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using testing::Matcher;
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using testing::NotNull;
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using testing::Property;
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using testing::SizeIs;
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Matcher<MCOperand> IsImm(int64_t Value) {
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return AllOf(Property(&MCOperand::isImm, Eq(true)),
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Property(&MCOperand::getImm, Eq(Value)));
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}
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Matcher<MCOperand> IsReg(unsigned Reg) {
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return AllOf(Property(&MCOperand::isReg, Eq(true)),
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Property(&MCOperand::getReg, Eq(Reg)));
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}
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Matcher<MCInst> OpcodeIs(unsigned Opcode) {
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return Property(&MCInst::getOpcode, Eq(Opcode));
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}
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Matcher<MCInst> IsMovImmediate(unsigned Opcode, int64_t Reg, int64_t Value) {
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return AllOf(OpcodeIs(Opcode), ElementsAre(IsReg(Reg), IsImm(Value)));
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}
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Matcher<MCInst> IsMovValueToStack(unsigned Opcode, int64_t Value,
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size_t Offset) {
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return AllOf(OpcodeIs(Opcode),
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ElementsAre(IsReg(X86::RSP), IsImm(1), IsReg(0), IsImm(Offset),
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IsReg(0), IsImm(Value)));
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}
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Matcher<MCInst> IsMovValueFromStack(unsigned Opcode, unsigned Reg) {
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return AllOf(OpcodeIs(Opcode),
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ElementsAre(IsReg(Reg), IsReg(X86::RSP), IsImm(1), IsReg(0),
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IsImm(0), IsReg(0)));
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}
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Matcher<MCInst> IsStackAllocate(unsigned Size) {
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return AllOf(OpcodeIs(X86::SUB64ri8),
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ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));
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}
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Matcher<MCInst> IsStackDeallocate(unsigned Size) {
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return AllOf(OpcodeIs(X86::ADD64ri8),
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ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));
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}
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constexpr const char kTriple[] = "x86_64-unknown-linux";
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class X86TargetTest : public ::testing::Test {
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protected:
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X86TargetTest(const char *Features) : State(kTriple, "core2", Features) {}
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static void SetUpTestCase() {
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LLVMInitializeX86TargetInfo();
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LLVMInitializeX86Target();
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LLVMInitializeX86TargetMC();
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InitializeX86ExegesisTarget();
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}
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std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
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return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
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Value);
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}
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const Instruction &getInstr(unsigned OpCode) {
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return State.getIC().getInstr(OpCode);
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}
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LLVMState State;
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};
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class Core2TargetTest : public X86TargetTest {
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public:
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Core2TargetTest() : X86TargetTest("") {}
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};
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class Core2AvxTargetTest : public X86TargetTest {
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public:
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Core2AvxTargetTest() : X86TargetTest("+avx") {}
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};
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class Core2Avx512TargetTest : public X86TargetTest {
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public:
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Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {}
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};
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TEST_F(Core2TargetTest, NoHighByteRegs) {
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EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH));
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}
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TEST_F(Core2TargetTest, SetFlags) {
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const unsigned Reg = X86::EFLAGS;
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EXPECT_THAT(setRegTo(Reg, APInt(64, 0x1111222233334444ULL)),
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ElementsAre(IsStackAllocate(8),
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IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
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OpcodeIs(X86::POPF64)));
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}
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TEST_F(Core2TargetTest, SetRegToGR8Value) {
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const uint8_t Value = 0xFFU;
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const unsigned Reg = X86::AL;
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EXPECT_THAT(setRegTo(Reg, APInt(8, Value)),
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ElementsAre(IsMovImmediate(X86::MOV8ri, Reg, Value)));
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}
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TEST_F(Core2TargetTest, SetRegToGR16Value) {
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const uint16_t Value = 0xFFFFU;
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const unsigned Reg = X86::BX;
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EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
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ElementsAre(IsMovImmediate(X86::MOV16ri, Reg, Value)));
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}
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TEST_F(Core2TargetTest, SetRegToGR32Value) {
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const uint32_t Value = 0x7FFFFU;
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const unsigned Reg = X86::ECX;
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EXPECT_THAT(setRegTo(Reg, APInt(32, Value)),
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ElementsAre(IsMovImmediate(X86::MOV32ri, Reg, Value)));
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}
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TEST_F(Core2TargetTest, SetRegToGR64Value) {
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const uint64_t Value = 0x7FFFFFFFFFFFFFFFULL;
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const unsigned Reg = X86::RDX;
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EXPECT_THAT(setRegTo(Reg, APInt(64, Value)),
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ElementsAre(IsMovImmediate(X86::MOV64ri, Reg, Value)));
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}
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TEST_F(Core2TargetTest, SetRegToVR64Value) {
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EXPECT_THAT(setRegTo(X86::MM0, APInt(64, 0x1111222233334444ULL)),
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ElementsAre(IsStackAllocate(8),
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IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
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IsMovValueFromStack(X86::MMX_MOVQ64rm, X86::MM0),
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IsStackDeallocate(8)));
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}
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TEST_F(Core2TargetTest, SetRegToVR128Value_Use_MOVDQUrm) {
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EXPECT_THAT(
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setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
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ElementsAre(IsStackAllocate(16),
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IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
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IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
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IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
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IsMovValueFromStack(X86::MOVDQUrm, X86::XMM0),
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IsStackDeallocate(16)));
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}
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TEST_F(Core2AvxTargetTest, SetRegToVR128Value_Use_VMOVDQUrm) {
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EXPECT_THAT(
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setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
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ElementsAre(IsStackAllocate(16),
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IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
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IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
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IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
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IsMovValueFromStack(X86::VMOVDQUrm, X86::XMM0),
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IsStackDeallocate(16)));
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}
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TEST_F(Core2Avx512TargetTest, SetRegToVR128Value_Use_VMOVDQU32Z128rm) {
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EXPECT_THAT(
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setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
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ElementsAre(IsStackAllocate(16),
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IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
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IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
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IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
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IsMovValueFromStack(X86::VMOVDQU32Z128rm, X86::XMM0),
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IsStackDeallocate(16)));
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}
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TEST_F(Core2AvxTargetTest, SetRegToVR256Value_Use_VMOVDQUYrm) {
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const char ValueStr[] =
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"1111111122222222333333334444444455555555666666667777777788888888";
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EXPECT_THAT(
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setRegTo(X86::YMM0, APInt(256, ValueStr, 16)),
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ElementsAreArray({IsStackAllocate(32),
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IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4),
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IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8),
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IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12),
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IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16),
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IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20),
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IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24),
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IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28),
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IsMovValueFromStack(X86::VMOVDQUYrm, X86::YMM0),
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IsStackDeallocate(32)}));
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}
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TEST_F(Core2Avx512TargetTest, SetRegToVR256Value_Use_VMOVDQU32Z256rm) {
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const char ValueStr[] =
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"1111111122222222333333334444444455555555666666667777777788888888";
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EXPECT_THAT(
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setRegTo(X86::YMM0, APInt(256, ValueStr, 16)),
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ElementsAreArray({IsStackAllocate(32),
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IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4),
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IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8),
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IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12),
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IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16),
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IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20),
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IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24),
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IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28),
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IsMovValueFromStack(X86::VMOVDQU32Z256rm, X86::YMM0),
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IsStackDeallocate(32)}));
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}
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TEST_F(Core2Avx512TargetTest, SetRegToVR512Value) {
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const char ValueStr[] =
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"1111111122222222333333334444444455555555666666667777777788888888"
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"99999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF00000000";
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EXPECT_THAT(
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setRegTo(X86::ZMM0, APInt(512, ValueStr, 16)),
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ElementsAreArray({IsStackAllocate(64),
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IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0xFFFFFFFFUL, 4),
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IsMovValueToStack(X86::MOV32mi, 0xEEEEEEEEUL, 8),
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IsMovValueToStack(X86::MOV32mi, 0xDDDDDDDDUL, 12),
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IsMovValueToStack(X86::MOV32mi, 0xCCCCCCCCUL, 16),
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IsMovValueToStack(X86::MOV32mi, 0xBBBBBBBBUL, 20),
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IsMovValueToStack(X86::MOV32mi, 0xAAAAAAAAUL, 24),
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IsMovValueToStack(X86::MOV32mi, 0x99999999UL, 28),
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IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 32),
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IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 36),
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IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 40),
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IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 44),
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IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 48),
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IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 52),
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IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 56),
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IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 60),
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IsMovValueFromStack(X86::VMOVDQU32Zrm, X86::ZMM0),
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IsStackDeallocate(64)}));
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}
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// Note: We always put 80 bits on the stack independently of the size of the
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// value. This uses a bit more space but makes the code simpler.
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TEST_F(Core2TargetTest, SetRegToST0_32Bits) {
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EXPECT_THAT(setRegTo(X86::ST0, APInt(32, 0x11112222ULL)),
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ElementsAre(IsStackAllocate(10),
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IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
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IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
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OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
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}
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TEST_F(Core2TargetTest, SetRegToST1_32Bits) {
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const MCInst CopySt0ToSt1 = MCInstBuilder(X86::ST_Frr).addReg(X86::ST1);
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EXPECT_THAT(setRegTo(X86::ST1, APInt(32, 0x11112222ULL)),
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ElementsAre(IsStackAllocate(10),
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IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
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IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
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IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
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OpcodeIs(X86::LD_F80m), CopySt0ToSt1,
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IsStackDeallocate(10)));
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}
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TEST_F(Core2TargetTest, SetRegToST0_64Bits) {
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EXPECT_THAT(setRegTo(X86::ST0, APInt(64, 0x1111222233334444ULL)),
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ElementsAre(IsStackAllocate(10),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
|
||
|
|
IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
|
||
|
|
OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(Core2TargetTest, SetRegToST0_80Bits) {
|
||
|
|
EXPECT_THAT(setRegTo(X86::ST0, APInt(80, "11112222333344445555", 16)),
|
||
|
|
ElementsAre(IsStackAllocate(10),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4),
|
||
|
|
IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8),
|
||
|
|
OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(Core2TargetTest, SetRegToFP0_80Bits) {
|
||
|
|
EXPECT_THAT(setRegTo(X86::FP0, APInt(80, "11112222333344445555", 16)),
|
||
|
|
ElementsAre(IsStackAllocate(10),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4),
|
||
|
|
IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8),
|
||
|
|
OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(Core2TargetTest, SetRegToFP1_32Bits) {
|
||
|
|
EXPECT_THAT(setRegTo(X86::FP1, APInt(32, 0x11112222ULL)),
|
||
|
|
ElementsAre(IsStackAllocate(10),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
|
||
|
|
IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
|
||
|
|
OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(Core2TargetTest, SetRegToFP1_4Bits) {
|
||
|
|
EXPECT_THAT(setRegTo(X86::FP1, APInt(4, 0x1ULL)),
|
||
|
|
ElementsAre(IsStackAllocate(10),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x00000001UL, 0),
|
||
|
|
IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
|
||
|
|
IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
|
||
|
|
OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
|
||
|
|
const Instruction &I = getInstr(X86::ADD64rm);
|
||
|
|
InstructionTemplate IT(&I);
|
||
|
|
constexpr const int kOffset = 42;
|
||
|
|
State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
|
||
|
|
// Memory is operands 2-6.
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[2]), IsReg(X86::RDI));
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[3]), IsImm(1));
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(0));
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(kOffset));
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) {
|
||
|
|
const Instruction &I = getInstr(X86::VGATHERDPSZ128rm);
|
||
|
|
InstructionTemplate IT(&I);
|
||
|
|
constexpr const int kOffset = 42;
|
||
|
|
State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
|
||
|
|
// Memory is operands 4-8.
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(X86::RDI));
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(1));
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0));
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[7]), IsImm(kOffset));
|
||
|
|
EXPECT_THAT(IT.getValueFor(I.Operands[8]), IsReg(0));
|
||
|
|
}
|
||
|
|
|
||
|
|
TEST_F(Core2TargetTest, AllowAsBackToBack) {
|
||
|
|
EXPECT_TRUE(
|
||
|
|
State.getExegesisTarget().allowAsBackToBack(getInstr(X86::ADD64rr)));
|
||
|
|
EXPECT_FALSE(
|
||
|
|
State.getExegesisTarget().allowAsBackToBack(getInstr(X86::LEA64r)));
|
||
|
|
}
|
||
|
|
|
||
|
|
} // namespace
|
||
|
|
} // namespace exegesis
|
||
|
|
} // namespace llvm
|