363 lines
15 KiB
LLVM
363 lines
15 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine -S %s | FileCheck %s
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; Check that we simplify llvm.umul.with.overflow, if the overflow check is
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; weakened by or (icmp ne %res, 0) %overflow. This is generated by code using
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; __builtin_mul_overflow with negative integer constants, e.g.
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; bool test(unsigned long long v, unsigned long long *res) {
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; return __builtin_mul_overflow(v, -4775807LL, res);
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; }
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declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #0
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define i1 @test1(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: store i64 [[MUL]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = or i1 %overflow, %cmp
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store i64 %mul, i64* %ptr, align 8
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ret i1 %overflow.1
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}
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define i1 @test1_logical(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test1_logical(
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; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: store i64 [[MUL]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = select i1 %overflow, i1 true, i1 %cmp
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store i64 %mul, i64* %ptr, align 8
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ret i1 %overflow.1
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}
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define i1 @test1_or_ops_swapped(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test1_or_ops_swapped(
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; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: store i64 [[MUL]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = or i1 %cmp, %overflow
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store i64 %mul, i64* %ptr, align 8
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ret i1 %overflow.1
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}
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define i1 @test1_or_ops_swapped_logical(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test1_or_ops_swapped_logical(
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; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: store i64 [[MUL]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = select i1 %cmp, i1 true, i1 %overflow
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store i64 %mul, i64* %ptr, align 8
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ret i1 %overflow.1
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}
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define i1 @test2(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
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; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = or i1 %overflow, %cmp
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%neg = sub i64 0, %mul
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store i64 %neg, i64* %ptr, align 8
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ret i1 %overflow.1
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}
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define i1 @test2_logical(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test2_logical(
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; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
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; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = select i1 %overflow, i1 true, i1 %cmp
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%neg = sub i64 0, %mul
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store i64 %neg, i64* %ptr, align 8
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ret i1 %overflow.1
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}
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declare void @use(i1)
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define i1 @test3_multiple_overflow_users(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test3_multiple_overflow_users(
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; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]])
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; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: call void @use(i1 [[OVERFLOW]])
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = or i1 %overflow, %cmp
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call void @use(i1 %overflow)
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ret i1 %overflow.1
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}
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define i1 @test3_multiple_overflow_users_logical(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test3_multiple_overflow_users_logical(
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; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]])
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; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: call void @use(i1 [[OVERFLOW]])
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = select i1 %overflow, i1 true, i1 %cmp
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call void @use(i1 %overflow)
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ret i1 %overflow.1
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}
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; Do not simplify if %overflow and %mul have multiple uses.
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define i1 @test3_multiple_overflow_and_mul_users(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test3_multiple_overflow_and_mul_users(
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; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]])
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; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1
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; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[MUL]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = or i1 [[OVERFLOW]], [[CMP]]
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; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
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; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: call void @use(i1 [[OVERFLOW]])
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = or i1 %overflow, %cmp
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%neg = sub i64 0, %mul
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store i64 %neg, i64* %ptr, align 8
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call void @use(i1 %overflow)
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ret i1 %overflow.1
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}
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define i1 @test3_multiple_overflow_and_mul_users_logical(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test3_multiple_overflow_and_mul_users_logical(
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; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]])
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; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1
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; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[MUL]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = or i1 [[OVERFLOW]], [[CMP]]
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; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
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; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: call void @use(i1 [[OVERFLOW]])
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = select i1 %overflow, i1 true, i1 %cmp
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%neg = sub i64 0, %mul
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store i64 %neg, i64* %ptr, align 8
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call void @use(i1 %overflow)
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ret i1 %overflow.1
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}
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declare void @use.2({ i64, i1 })
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define i1 @test3_multiple_res_users(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test3_multiple_res_users(
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; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]])
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; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
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; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: call void @use.2({ i64, i1 } [[RES]])
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = or i1 %overflow, %cmp
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%neg = sub i64 0, %mul
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store i64 %neg, i64* %ptr, align 8
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call void @use.2({ i64, i1 } %res)
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ret i1 %overflow.1
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}
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define i1 @test3_multiple_res_users_logical(i64 %a, i64 %b, i64* %ptr) {
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; CHECK-LABEL: @test3_multiple_res_users_logical(
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; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]])
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; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
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; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
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; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
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; CHECK-NEXT: call void @use.2({ i64, i1 } [[RES]])
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; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
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;
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%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
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%overflow = extractvalue { i64, i1 } %res, 1
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%mul = extractvalue { i64, i1 } %res, 0
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%cmp = icmp ne i64 %mul, 0
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%overflow.1 = select i1 %overflow, i1 true, i1 %cmp
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%neg = sub i64 0, %mul
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store i64 %neg, i64* %ptr, align 8
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call void @use.2({ i64, i1 } %res)
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ret i1 %overflow.1
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}
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declare void @use.3(i64)
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; Simplify if %mul has multiple uses.
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define i1 @test3_multiple_mul_users(i64 %a, i64 %b, i64* %ptr) {
|
||
|
|
; CHECK-LABEL: @test3_multiple_mul_users(
|
||
|
|
; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]]
|
||
|
|
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
|
||
|
|
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
|
||
|
|
; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
|
||
|
|
; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
|
||
|
|
; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
|
||
|
|
; CHECK-NEXT: call void @use.3(i64 [[MUL]])
|
||
|
|
; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
|
||
|
|
;
|
||
|
|
|
||
|
|
%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
|
||
|
|
%overflow = extractvalue { i64, i1 } %res, 1
|
||
|
|
%mul = extractvalue { i64, i1 } %res, 0
|
||
|
|
%cmp = icmp ne i64 %mul, 0
|
||
|
|
%overflow.1 = or i1 %overflow, %cmp
|
||
|
|
%neg = sub i64 0, %mul
|
||
|
|
store i64 %neg, i64* %ptr, align 8
|
||
|
|
call void @use.3(i64 %mul)
|
||
|
|
ret i1 %overflow.1
|
||
|
|
}
|
||
|
|
|
||
|
|
define i1 @test3_multiple_mul_users_logical(i64 %a, i64 %b, i64* %ptr) {
|
||
|
|
; CHECK-LABEL: @test3_multiple_mul_users_logical(
|
||
|
|
; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B:%.*]]
|
||
|
|
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0
|
||
|
|
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0
|
||
|
|
; CHECK-NEXT: [[OVERFLOW_1:%.*]] = and i1 [[TMP1]], [[TMP2]]
|
||
|
|
; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
|
||
|
|
; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
|
||
|
|
; CHECK-NEXT: call void @use.3(i64 [[MUL]])
|
||
|
|
; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
|
||
|
|
;
|
||
|
|
|
||
|
|
%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
|
||
|
|
%overflow = extractvalue { i64, i1 } %res, 1
|
||
|
|
%mul = extractvalue { i64, i1 } %res, 0
|
||
|
|
%cmp = icmp ne i64 %mul, 0
|
||
|
|
%overflow.1 = select i1 %overflow, i1 true, i1 %cmp
|
||
|
|
%neg = sub i64 0, %mul
|
||
|
|
store i64 %neg, i64* %ptr, align 8
|
||
|
|
call void @use.3(i64 %mul)
|
||
|
|
ret i1 %overflow.1
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
define i1 @test4_no_icmp_ne(i64 %a, i64 %b, i64* %ptr) {
|
||
|
|
; CHECK-LABEL: @test4_no_icmp_ne(
|
||
|
|
; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]])
|
||
|
|
; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1
|
||
|
|
; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0
|
||
|
|
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[MUL]], 0
|
||
|
|
; CHECK-NEXT: [[OVERFLOW_1:%.*]] = or i1 [[OVERFLOW]], [[CMP]]
|
||
|
|
; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
|
||
|
|
; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
|
||
|
|
; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
|
||
|
|
;
|
||
|
|
%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
|
||
|
|
%overflow = extractvalue { i64, i1 } %res, 1
|
||
|
|
%mul = extractvalue { i64, i1 } %res, 0
|
||
|
|
%cmp = icmp sgt i64 %mul, 0
|
||
|
|
%overflow.1 = or i1 %overflow, %cmp
|
||
|
|
%neg = sub i64 0, %mul
|
||
|
|
store i64 %neg, i64* %ptr, align 8
|
||
|
|
ret i1 %overflow.1
|
||
|
|
}
|
||
|
|
|
||
|
|
define i1 @test4_no_icmp_ne_logical(i64 %a, i64 %b, i64* %ptr) {
|
||
|
|
; CHECK-LABEL: @test4_no_icmp_ne_logical(
|
||
|
|
; CHECK-NEXT: [[RES:%.*]] = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A:%.*]], i64 [[B:%.*]])
|
||
|
|
; CHECK-NEXT: [[OVERFLOW:%.*]] = extractvalue { i64, i1 } [[RES]], 1
|
||
|
|
; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i64, i1 } [[RES]], 0
|
||
|
|
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i64 [[MUL]], 0
|
||
|
|
; CHECK-NEXT: [[OVERFLOW_1:%.*]] = or i1 [[OVERFLOW]], [[CMP]]
|
||
|
|
; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
|
||
|
|
; CHECK-NEXT: store i64 [[NEG]], i64* [[PTR:%.*]], align 8
|
||
|
|
; CHECK-NEXT: ret i1 [[OVERFLOW_1]]
|
||
|
|
;
|
||
|
|
%res = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
|
||
|
|
%overflow = extractvalue { i64, i1 } %res, 1
|
||
|
|
%mul = extractvalue { i64, i1 } %res, 0
|
||
|
|
%cmp = icmp sgt i64 %mul, 0
|
||
|
|
%overflow.1 = select i1 %overflow, i1 true, i1 %cmp
|
||
|
|
%neg = sub i64 0, %mul
|
||
|
|
store i64 %neg, i64* %ptr, align 8
|
||
|
|
ret i1 %overflow.1
|
||
|
|
}
|
||
|
|
|
||
|
|
attributes #0 = { nounwind readnone speculatable willreturn }
|