201 lines
6.3 KiB
LLVM
201 lines
6.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; Given pattern:
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; (trunc (iSrc x l>> Q) to iDst) l>> K
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; we should rewrite it as
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; (trunc (iSrc x l>> (Q+K)) to iDst)
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; iff (Q+K) is bitwidth(iSrc)-1
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; THIS FOLD DOES *NOT* REQUIRE ANY 'nuw'/`nsw` FLAGS!
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; Basic scalar test
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define i16 @t0(i32 %x, i16 %y) {
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; CHECK-LABEL: @t0(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
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; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[TMP1]] to i16
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = lshr i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -1
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%t5 = lshr i16 %t3, %t4
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ret i16 %t5
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}
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; Basic vector tests
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define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) {
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; CHECK-LABEL: @t1_vec_splat(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 31, i32 31>
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; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[T5]]
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;
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%t0 = sub <2 x i16> <i16 32, i16 32>, %y
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%t1 = zext <2 x i16> %t0 to <2 x i32>
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%t2 = lshr <2 x i32> %x, %t1
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%t3 = trunc <2 x i32> %t2 to <2 x i16>
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%t4 = add <2 x i16> %y, <i16 -1, i16 -1>
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%t5 = lshr <2 x i16> %t3, %t4
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ret <2 x i16> %t5
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}
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define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t3_vec_nonsplat_undef0(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 31, i32 0, i32 31>
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; CHECK-NEXT: [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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%t1 = zext <3 x i16> %t0 to <3 x i32>
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%t2 = lshr <3 x i32> %x, %t1
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%t3 = trunc <3 x i32> %t2 to <3 x i16>
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%t4 = add <3 x i16> %y, <i16 -1, i16 -1, i16 -1>
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%t5 = lshr <3 x i16> %t3, %t4
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ret <3 x i16> %t5
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}
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define <3 x i16> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t4_vec_nonsplat_undef1(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 31, i32 0, i32 31>
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; CHECK-NEXT: [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 32, i16 32>, %y
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%t1 = zext <3 x i16> %t0 to <3 x i32>
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%t2 = lshr <3 x i32> %x, %t1
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%t3 = trunc <3 x i32> %t2 to <3 x i16>
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%t4 = add <3 x i16> %y, <i16 -1, i16 undef, i16 -1>
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%t5 = lshr <3 x i16> %t3, %t4
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ret <3 x i16> %t5
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}
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define <3 x i16> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t5_vec_nonsplat_undef1(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr <3 x i32> [[X:%.*]], <i32 31, i32 0, i32 31>
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; CHECK-NEXT: [[T5:%.*]] = trunc <3 x i32> [[TMP1]] to <3 x i16>
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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%t1 = zext <3 x i16> %t0 to <3 x i32>
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%t2 = lshr <3 x i32> %x, %t1
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%t3 = trunc <3 x i32> %t2 to <3 x i16>
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%t4 = add <3 x i16> %y, <i16 -1, i16 undef, i16 -1>
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%t5 = lshr <3 x i16> %t3, %t4
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ret <3 x i16> %t5
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}
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; One-use tests
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declare void @use16(i16)
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declare void @use32(i32)
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define i16 @t6_extrause0(i32 %x, i16 %y) {
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; CHECK-LABEL: @t6_extrause0(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: call void @use16(i16 [[T3]])
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X]], 31
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; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[TMP1]] to i16
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = lshr i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -1
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call void @use16(i16 %t3)
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%t5 = lshr i16 %t3, %t4
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ret i16 %t5
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}
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define i16 @t7_extrause1(i32 %x, i16 %y) {
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; CHECK-LABEL: @t7_extrause1(
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y:%.*]], -1
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; CHECK-NEXT: call void @use16(i16 [[T4]])
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31
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; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[TMP1]] to i16
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = lshr i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -1
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call void @use16(i16 %t4)
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%t5 = lshr i16 %t3, %t4
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ret i16 %t5
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}
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define i16 @t8_extrause2(i32 %x, i16 %y) {
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; CHECK-LABEL: @t8_extrause2(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -1
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; CHECK-NEXT: call void @use16(i16 [[T3]])
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; CHECK-NEXT: call void @use16(i16 [[T4]])
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; CHECK-NEXT: [[T5:%.*]] = lshr i16 [[T3]], [[T4]]
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = lshr i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -1
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call void @use16(i16 %t3)
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call void @use16(i16 %t4)
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%t5 = lshr i16 %t3, %t4
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ret i16 %t5
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}
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; No 'nuw'/'nsw' flags are to be propagated!
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; But we can't test that, such IR does not reach that code.
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; Negative tests
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; Can only fold if we are extracting the sign bit.
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define i16 @t9_lshr(i32 %x, i16 %y) {
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; CHECK-LABEL: @t9_lshr(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -2
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; CHECK-NEXT: [[T5:%.*]] = lshr i16 [[T3]], [[T4]]
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = lshr i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -2
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%t5 = lshr i16 %t3, %t4
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ret i16 %t5
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}
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; If we have different right-shifts, in general, we can't do anything with it.
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define i16 @n10_ashr_lshr(i32 %x, i16 %y) {
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; CHECK-LABEL: @n10_ashr_lshr(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -1
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; CHECK-NEXT: [[T5:%.*]] = lshr i16 [[T3]], [[T4]]
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = ashr i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -1
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%t5 = lshr i16 %t3, %t4
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ret i16 %t5
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}
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