200 lines
8.0 KiB
LLVM
200 lines
8.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; If we have some pattern that leaves only some low bits set, and then performs
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; left-shift of those bits, we can combine those two shifts into a shift+mask.
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; There are many variants to this pattern:
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; a) (trunc (x & ((1 << maskNbits) - 1))) << shiftNbits
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; simplify to:
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; (trunc(x)) << shiftNbits
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; Simple tests.
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declare void @use32(i32)
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declare void @use64(i64)
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define i32 @t0_basic(i64 %x, i32 %nbits) {
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; CHECK-LABEL: @t0_basic(
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; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
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; CHECK-NEXT: [[T1:%.*]] = shl i64 1, [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i64 [[T1]], -1
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; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
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; CHECK-NEXT: [[T4:%.*]] = and i64 [[T2]], [[X:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[NBITS]])
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; CHECK-NEXT: call void @use64(i64 [[T0]])
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; CHECK-NEXT: call void @use64(i64 [[T1]])
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; CHECK-NEXT: call void @use64(i64 [[T2]])
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; CHECK-NEXT: call void @use32(i32 [[T3]])
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; CHECK-NEXT: call void @use64(i64 [[T4]])
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X]] to i32
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; CHECK-NEXT: [[T6:%.*]] = shl i32 [[TMP1]], [[T3]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = zext i32 %nbits to i64
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%t1 = shl i64 1, %t0
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%t2 = add i64 %t1, -1
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%t3 = sub i32 32, %nbits
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%t4 = and i64 %t2, %x
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call void @use32(i32 %nbits)
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call void @use64(i64 %t0)
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call void @use64(i64 %t1)
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call void @use64(i64 %t2)
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call void @use32(i32 %t3)
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call void @use64(i64 %t4)
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%t5 = trunc i64 %t4 to i32
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%t6 = shl i32 %t5, %t3
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ret i32 %t6
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}
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; Vectors
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declare void @use8xi32(<8 x i32>)
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declare void @use8xi64(<8 x i64>)
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define <8 x i32> @t1_vec_splat(<8 x i64> %x, <8 x i32> %nbits) {
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; CHECK-LABEL: @t1_vec_splat(
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; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
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; CHECK-NEXT: [[T1:%.*]] = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>, [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add <8 x i64> [[T1]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
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; CHECK-NEXT: [[T3:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]]
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; CHECK-NEXT: [[T4:%.*]] = and <8 x i64> [[T2]], [[X:%.*]]
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[NBITS]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T2]])
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T4]])
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; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X]] to <8 x i32>
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; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
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; CHECK-NEXT: ret <8 x i32> [[T6]]
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;
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%t0 = zext <8 x i32> %nbits to <8 x i64>
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%t1 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>, %t0
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%t2 = add <8 x i64> %t1, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
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%t3 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, %nbits
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%t4 = and <8 x i64> %t2, %x
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call void @use8xi32(<8 x i32> %nbits)
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call void @use8xi64(<8 x i64> %t0)
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call void @use8xi64(<8 x i64> %t1)
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call void @use8xi64(<8 x i64> %t2)
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call void @use8xi32(<8 x i32> %t3)
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call void @use8xi64(<8 x i64> %t4)
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%t5 = trunc <8 x i64> %t4 to <8 x i32>
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%t6 = shl <8 x i32> %t5, %t3
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ret <8 x i32> %t6
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}
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define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) {
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; CHECK-LABEL: @t2_vec_splat_undef(
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; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
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; CHECK-NEXT: [[T1:%.*]] = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 undef, i64 1>, [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add <8 x i64> [[T1]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>
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; CHECK-NEXT: [[T3:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, [[NBITS]]
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; CHECK-NEXT: [[T4:%.*]] = and <8 x i64> [[T2]], [[X:%.*]]
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[NBITS]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T2]])
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T4]])
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; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X]] to <8 x i32>
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; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
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; CHECK-NEXT: ret <8 x i32> [[T6]]
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;
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%t0 = zext <8 x i32> %nbits to <8 x i64>
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%t1 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 undef, i64 1>, %t0
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%t2 = add <8 x i64> %t1, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>
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%t3 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 undef, i32 32>, %nbits
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%t4 = and <8 x i64> %t2, %x
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call void @use8xi32(<8 x i32> %nbits)
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call void @use8xi64(<8 x i64> %t0)
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call void @use8xi64(<8 x i64> %t1)
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call void @use8xi64(<8 x i64> %t2)
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call void @use8xi32(<8 x i32> %t3)
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call void @use8xi64(<8 x i64> %t4)
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%t5 = trunc <8 x i64> %t4 to <8 x i32>
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%t6 = shl <8 x i32> %t5, %t3
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ret <8 x i32> %t6
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}
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define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) {
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; CHECK-LABEL: @t3_vec_nonsplat(
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; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
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; CHECK-NEXT: [[T1:%.*]] = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>, [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add <8 x i64> [[T1]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
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; CHECK-NEXT: [[T3:%.*]] = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, [[NBITS]]
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; CHECK-NEXT: [[T4:%.*]] = and <8 x i64> [[T2]], [[X:%.*]]
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[NBITS]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T2]])
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T3]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T4]])
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; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X]] to <8 x i32>
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; CHECK-NEXT: [[T6:%.*]] = shl <8 x i32> [[TMP1]], [[T3]]
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; CHECK-NEXT: ret <8 x i32> [[T6]]
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;
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%t0 = zext <8 x i32> %nbits to <8 x i64>
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%t1 = shl <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>, %t0
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%t2 = add <8 x i64> %t1, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
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%t3 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, %nbits
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%t4 = and <8 x i64> %t2, %x
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call void @use8xi32(<8 x i32> %nbits)
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call void @use8xi64(<8 x i64> %t0)
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call void @use8xi64(<8 x i64> %t1)
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call void @use8xi64(<8 x i64> %t2)
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call void @use8xi32(<8 x i32> %t3)
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call void @use8xi64(<8 x i64> %t4)
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%t5 = trunc <8 x i64> %t4 to <8 x i32>
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%t6 = shl <8 x i32> %t5, %t3
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ret <8 x i32> %t6
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}
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; Extra uses
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define i32 @n4_extrause(i64 %x, i32 %nbits) {
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; CHECK-LABEL: @n4_extrause(
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; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
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; CHECK-NEXT: [[T1:%.*]] = shl i64 1, [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i64 [[T1]], -1
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; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
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; CHECK-NEXT: [[T4:%.*]] = and i64 [[T2]], [[X:%.*]]
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; CHECK-NEXT: call void @use32(i32 [[NBITS]])
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; CHECK-NEXT: call void @use64(i64 [[T0]])
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; CHECK-NEXT: call void @use64(i64 [[T1]])
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; CHECK-NEXT: call void @use64(i64 [[T2]])
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; CHECK-NEXT: call void @use32(i32 [[T3]])
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; CHECK-NEXT: call void @use64(i64 [[T4]])
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; CHECK-NEXT: [[T5:%.*]] = trunc i64 [[T4]] to i32
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; CHECK-NEXT: call void @use32(i32 [[T5]])
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; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T5]], [[T3]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = zext i32 %nbits to i64
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%t1 = shl i64 1, %t0
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%t2 = add i64 %t1, -1
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%t3 = sub i32 32, %nbits
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%t4 = and i64 %t2, %x
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call void @use32(i32 %nbits)
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call void @use64(i64 %t0)
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call void @use64(i64 %t1)
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call void @use64(i64 %t2)
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call void @use32(i32 %t3)
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call void @use64(i64 %t4)
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%t5 = trunc i64 %t4 to i32
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call void @use32(i32 %t5)
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%t6 = shl i32 %t5, %t3
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ret i32 %t6
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}
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