220 lines
8.2 KiB
LLVM
220 lines
8.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; If we have some pattern that leaves only some low bits set, lshr then performs
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; left-shift of those bits, we can combine those two shifts into a shift+mask.
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; There are many variants to this pattern:
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; e) (trunc (((x << maskNbits) l>> maskNbits))) << shiftNbits
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; simplify to:
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; ((trunc(x)) << shiftNbits) & (-1 >> ((-(maskNbits+shiftNbits))+32))
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; Simple tests.
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declare void @use32(i32)
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declare void @use64(i64)
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define i32 @t0_basic(i64 %x, i32 %nbits) {
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; CHECK-LABEL: @t0_basic(
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; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
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; CHECK-NEXT: [[T1:%.*]] = shl i64 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33
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; CHECK-NEXT: call void @use64(i64 [[T0]])
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; CHECK-NEXT: call void @use64(i64 [[T1]])
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X]] to i32
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; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], [[T2]]
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; CHECK-NEXT: [[T5:%.*]] = and i32 [[TMP2]], 2147483647
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; CHECK-NEXT: ret i32 [[T5]]
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;
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%t0 = zext i32 %nbits to i64
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%t1 = shl i64 %x, %t0
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%t2 = add i32 %nbits, -33
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call void @use64(i64 %t0)
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call void @use64(i64 %t1)
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call void @use32(i32 %t2)
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%t3 = lshr i64 %t1, %t0
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%t4 = trunc i64 %t3 to i32
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%t5 = shl i32 %t4, %t2 ; shift is smaller than mask
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ret i32 %t5
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}
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; Vectors
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declare void @use8xi32(<8 x i32>)
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declare void @use8xi64(<8 x i64>)
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define <8 x i32> @t1_vec_splat(<8 x i64> %x, <8 x i32> %nbits) {
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; CHECK-LABEL: @t1_vec_splat(
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; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
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; CHECK-NEXT: [[T1:%.*]] = shl <8 x i64> [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33>
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
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; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X]] to <8 x i32>
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; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]]
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; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
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; CHECK-NEXT: ret <8 x i32> [[T5]]
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;
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%t0 = zext <8 x i32> %nbits to <8 x i64>
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%t1 = shl <8 x i64> %x, %t0
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%t2 = add <8 x i32> %nbits, <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33>
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call void @use8xi64(<8 x i64> %t0)
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call void @use8xi64(<8 x i64> %t1)
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call void @use8xi32(<8 x i32> %t2)
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%t3 = lshr <8 x i64> %t1, %t0
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%t4 = trunc <8 x i64> %t3 to <8 x i32>
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%t5 = shl <8 x i32> %t4, %t2 ; shift is smaller than mask
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ret <8 x i32> %t5
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}
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define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) {
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; CHECK-LABEL: @t2_vec_splat_undef(
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; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
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; CHECK-NEXT: [[T1:%.*]] = shl <8 x i64> [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 undef, i32 -33>
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
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; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X]] to <8 x i32>
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; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]]
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; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 undef, i32 2147483647>
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; CHECK-NEXT: ret <8 x i32> [[T5]]
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;
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%t0 = zext <8 x i32> %nbits to <8 x i64>
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%t1 = shl <8 x i64> %x, %t0
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%t2 = add <8 x i32> %nbits, <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 undef, i32 -33>
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call void @use8xi64(<8 x i64> %t0)
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call void @use8xi64(<8 x i64> %t1)
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call void @use8xi32(<8 x i32> %t2)
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%t3 = lshr <8 x i64> %t1, %t0
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%t4 = trunc <8 x i64> %t3 to <8 x i32>
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%t5 = shl <8 x i32> %t4, %t2 ; shift is smaller than mask
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ret <8 x i32> %t5
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}
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define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) {
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; CHECK-LABEL: @t3_vec_nonsplat(
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; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
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; CHECK-NEXT: [[T1:%.*]] = shl <8 x i64> [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -64, i32 -63, i32 -33, i32 -32, i32 63, i32 64, i32 undef, i32 65>
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
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; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
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; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
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; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X]] to <8 x i32>
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; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]]
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; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], <i32 undef, i32 1, i32 2147483647, i32 -1, i32 -1, i32 -1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <8 x i32> [[T5]]
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;
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%t0 = zext <8 x i32> %nbits to <8 x i64>
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%t1 = shl <8 x i64> %x, %t0
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%t2 = add <8 x i32> %nbits, <i32 -64, i32 -63, i32 -33, i32 -32, i32 63, i32 64, i32 undef, i32 65>
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call void @use8xi64(<8 x i64> %t0)
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call void @use8xi64(<8 x i64> %t1)
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call void @use8xi32(<8 x i32> %t2)
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%t3 = lshr <8 x i64> %t1, %t0
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%t4 = trunc <8 x i64> %t3 to <8 x i32>
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%t5 = shl <8 x i32> %t4, %t2 ; shift is smaller than mask
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ret <8 x i32> %t5
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}
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; Extra uses.
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define i32 @n4_extrause0(i64 %x, i32 %nbits) {
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; CHECK-LABEL: @n4_extrause0(
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; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
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; CHECK-NEXT: [[T1:%.*]] = shl i64 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33
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; CHECK-NEXT: call void @use64(i64 [[T0]])
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; CHECK-NEXT: call void @use64(i64 [[T1]])
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[T1]], [[T0]]
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; CHECK-NEXT: call void @use64(i64 [[T3]])
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; CHECK-NEXT: [[T4:%.*]] = trunc i64 [[T3]] to i32
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; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T4]], [[T2]]
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; CHECK-NEXT: ret i32 [[T5]]
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;
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%t0 = zext i32 %nbits to i64
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%t1 = shl i64 %x, %t0
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%t2 = add i32 %nbits, -33
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call void @use64(i64 %t0)
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call void @use64(i64 %t1)
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call void @use32(i32 %t2)
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%t3 = lshr i64 %t1, %t0
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call void @use64(i64 %t3)
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%t4 = trunc i64 %t3 to i32
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%t5 = shl i32 %t4, %t2 ; shift is smaller than mask
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ret i32 %t5
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}
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define i32 @n5_extrause1(i64 %x, i32 %nbits) {
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; CHECK-LABEL: @n5_extrause1(
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; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
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; CHECK-NEXT: [[T1:%.*]] = shl i64 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33
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; CHECK-NEXT: call void @use64(i64 [[T0]])
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; CHECK-NEXT: call void @use64(i64 [[T1]])
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[T1]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = trunc i64 [[T3]] to i32
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; CHECK-NEXT: call void @use32(i32 [[T4]])
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; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T4]], [[T2]]
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; CHECK-NEXT: ret i32 [[T5]]
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;
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%t0 = zext i32 %nbits to i64
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%t1 = shl i64 %x, %t0
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%t2 = add i32 %nbits, -33
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call void @use64(i64 %t0)
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call void @use64(i64 %t1)
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call void @use32(i32 %t2)
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%t3 = lshr i64 %t1, %t0
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%t4 = trunc i64 %t3 to i32
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call void @use32(i32 %t4)
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%t5 = shl i32 %t4, %t2 ; shift is smaller than mask
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ret i32 %t5
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}
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define i32 @n6_extrause2(i64 %x, i32 %nbits) {
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; CHECK-LABEL: @n6_extrause2(
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; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
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; CHECK-NEXT: [[T1:%.*]] = shl i64 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33
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; CHECK-NEXT: call void @use64(i64 [[T0]])
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; CHECK-NEXT: call void @use64(i64 [[T1]])
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = lshr i64 [[T1]], [[T0]]
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; CHECK-NEXT: call void @use64(i64 [[T3]])
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; CHECK-NEXT: [[T4:%.*]] = trunc i64 [[T3]] to i32
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; CHECK-NEXT: call void @use32(i32 [[T4]])
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; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T4]], [[T2]]
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; CHECK-NEXT: ret i32 [[T5]]
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;
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%t0 = zext i32 %nbits to i64
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%t1 = shl i64 %x, %t0
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%t2 = add i32 %nbits, -33
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call void @use64(i64 %t0)
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call void @use64(i64 %t1)
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call void @use32(i32 %t2)
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%t3 = lshr i64 %t1, %t0
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call void @use64(i64 %t3)
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%t4 = trunc i64 %t3 to i32
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call void @use32(i32 %t4)
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%t5 = shl i32 %t4, %t2 ; shift is smaller than mask
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ret i32 %t5
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}
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