124 lines
3.6 KiB
LLVM
124 lines
3.6 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -S -indvars | FileCheck %s
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declare i32 @llvm.uadd.sat.i32(i32, i32)
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declare i32 @llvm.sadd.sat.i32(i32, i32)
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declare i32 @llvm.usub.sat.i32(i32, i32)
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declare i32 @llvm.ssub.sat.i32(i32, i32)
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define void @uadd_sat(i32* %p) {
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; CHECK-LABEL: @uadd_sat(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[SAT1:%.*]] = add nuw nsw i32 [[I]], 1
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; CHECK-NEXT: store volatile i32 [[SAT1]], i32* [[P:%.*]]
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; CHECK-NEXT: [[I_INC]] = add nuw nsw i32 [[I]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[I_INC]], 100
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; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[END:%.*]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%i = phi i32 [ 0, %entry ], [ %i.inc, %loop ]
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%sat = call i32 @llvm.uadd.sat.i32(i32 %i, i32 1)
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store volatile i32 %sat, i32* %p
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%i.inc = add nuw nsw i32 %i, 1
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%cmp = icmp ne i32 %i.inc, 100
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br i1 %cmp, label %loop, label %end
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end:
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ret void
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}
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define void @sadd_sat(i32* %p) {
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; CHECK-LABEL: @sadd_sat(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[SAT1:%.*]] = add nuw nsw i32 [[I]], 1
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; CHECK-NEXT: store volatile i32 [[SAT1]], i32* [[P:%.*]]
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; CHECK-NEXT: [[I_INC]] = add nuw nsw i32 [[I]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[I_INC]], 100
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; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[END:%.*]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%i = phi i32 [ 0, %entry ], [ %i.inc, %loop ]
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%sat = call i32 @llvm.sadd.sat.i32(i32 %i, i32 1)
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store volatile i32 %sat, i32* %p
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%i.inc = add nuw nsw i32 %i, 1
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%cmp = icmp ne i32 %i.inc, 100
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br i1 %cmp, label %loop, label %end
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end:
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ret void
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}
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define void @usub_sat(i32* %p) {
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; CHECK-LABEL: @usub_sat(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[SAT1:%.*]] = sub nuw nsw i32 [[I]], 1
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; CHECK-NEXT: store volatile i32 [[SAT1]], i32* [[P:%.*]]
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; CHECK-NEXT: [[I_INC]] = add nuw nsw i32 [[I]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[I_INC]], 100
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; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[END:%.*]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%i = phi i32 [ 1, %entry ], [ %i.inc, %loop ]
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%sat = call i32 @llvm.usub.sat.i32(i32 %i, i32 1)
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store volatile i32 %sat, i32* %p
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%i.inc = add nuw nsw i32 %i, 1
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%cmp = icmp ne i32 %i.inc, 100
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br i1 %cmp, label %loop, label %end
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end:
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ret void
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}
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define void @ssub_sat(i32* %p) {
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; CHECK-LABEL: @ssub_sat(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[SAT1:%.*]] = sub nsw i32 [[I]], 1
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; CHECK-NEXT: store volatile i32 [[SAT1]], i32* [[P:%.*]]
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; CHECK-NEXT: [[I_INC]] = add nuw nsw i32 [[I]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[I_INC]], 100
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; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[END:%.*]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%i = phi i32 [ 0, %entry ], [ %i.inc, %loop ]
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%sat = call i32 @llvm.ssub.sat.i32(i32 %i, i32 1)
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store volatile i32 %sat, i32* %p
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%i.inc = add nuw nsw i32 %i, 1
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%cmp = icmp ne i32 %i.inc, 100
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br i1 %cmp, label %loop, label %end
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end:
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ret void
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}
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