80 lines
2.4 KiB
Plaintext
80 lines
2.4 KiB
Plaintext
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#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
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# REQUIRES: aarch64-registered-target
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--- |
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; ModuleID = 'test.ll'
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source_filename = "test.ll"
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-unknown"
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define i32 @test_phi(i32 %argc) {
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entry:
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%cmp = icmp ugt i32 %argc, 0
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br i1 %cmp, label %case1, label %case2
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case1: ; preds = %entry
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%tmp11 = add i32 %argc, 1
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br label %return
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case2: ; preds = %entry
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%tmp22 = add i32 %argc, 2
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br label %return
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return: ; preds = %case2, %case1
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%res = phi i32 [ %tmp11, %case1 ], [ %tmp22, %case2 ]
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ret i32 %res
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}
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...
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---
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name: test_phi
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legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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- { id: 3, class: _, preferred-register: '' }
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- { id: 4, class: _, preferred-register: '' }
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- { id: 5, class: _, preferred-register: '' }
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- { id: 6, class: _, preferred-register: '' }
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- { id: 7, class: _, preferred-register: '' }
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- { id: 8, class: _, preferred-register: '' }
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- { id: 9, class: _, preferred-register: '' }
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liveins:
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body: |
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bb.1.entry:
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successors: %bb.2.case1(0x40000000), %bb.3.case2(0x40000000)
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liveins: $w0
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; This test makes sure that the Verifier catches G_PHI with mismatching types.
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; CHECK: Bad machine code: Generic Instruction G_PHI has operands with incompatible/missing types
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%0(s32) = COPY $w0
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%1(s32) = G_CONSTANT i32 0
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%3(s32) = G_CONSTANT i32 1
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%5(s32) = G_CONSTANT i32 2
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%8(s32) = G_ICMP intpred(ugt), %0(s32), %1
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%2(s1) = G_TRUNC %8(s32)
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G_BRCOND %2(s1), %bb.2.case1
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G_BR %bb.3.case2
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bb.2.case1:
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successors: %bb.4.return(0x80000000)
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%4(s32) = G_ADD %0, %3
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%9(s16) = G_TRUNC %4(s32)
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G_BR %bb.4.return
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bb.3.case2:
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successors: %bb.4.return(0x80000000)
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%6(s32) = G_ADD %0, %5
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bb.4.return:
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%7(s32) = G_PHI %9(s16), %bb.2.case1, %6(s32), %bb.3.case2
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$w0 = COPY %7(s32)
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RET_ReallyLR implicit $w0
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...
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