100 lines
3.8 KiB
ArmAsm
100 lines
3.8 KiB
ArmAsm
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfh -riscv-no-aliases \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfh \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfh -riscv-no-aliases \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfh \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfh < %s \
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# RUN: | llvm-objdump -d --mattr=+experimental-zfh -M no-aliases - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-zfh < %s \
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# RUN: | llvm-objdump -d --mattr=+experimental-zfh - \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfh < %s \
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# RUN: | llvm-objdump -d --mattr=+experimental-zfh -M no-aliases - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-zfh < %s \
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# RUN: | llvm-objdump -d --mattr=+experimental-zfh - \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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##===----------------------------------------------------------------------===##
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## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
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##===----------------------------------------------------------------------===##
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# CHECK-INST: fsgnj.h ft0, ft1, ft1
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# CHECK-ALIAS: fmv.h ft0, ft1
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fmv.h f0, f1
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# CHECK-INST: fsgnjx.h ft1, ft2, ft2
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# CHECK-ALIAS: fabs.h ft1, ft2
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fabs.h f1, f2
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# CHECK-INST: fsgnjn.h ft2, ft3, ft3
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# CHECK-ALIAS: fneg.h ft2, ft3
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fneg.h f2, f3
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# CHECK-INST: flt.h tp, ft6, ft5
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# CHECK-ALIAS: flt.h tp, ft6, ft5
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fgt.h x4, f5, f6
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# CHECK-INST: fle.h t2, fs1, fs0
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# CHECK-ALIAS: fle.h t2, fs1, fs0
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fge.h x7, f8, f9
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# CHECK-INST: fmv.x.h a2, fs7
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# CHECK-ALIAS: fmv.x.h a2, fs7
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fmv.x.h a2, fs7
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# CHECK-INST: fmv.h.x ft1, a6
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# CHECK-ALIAS: fmv.h.x ft1, a6
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fmv.h.x ft1, a6
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# CHECK-INST: flh ft0, 0(a0)
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# CHECK-ALIAS: flh ft0, 0(a0)
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flh f0, (x10)
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# CHECK-INST: fsh ft0, 0(a0)
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# CHECK-ALIAS: fsh ft0, 0(a0)
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fsh f0, (x10)
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##===----------------------------------------------------------------------===##
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## Aliases which omit the rounding mode.
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##===----------------------------------------------------------------------===##
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# CHECK-INST: fmadd.h fa0, fa1, fa2, fa3, dyn
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# CHECK-ALIAS: fmadd.h fa0, fa1, fa2, fa3{{[[:space:]]}}
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fmadd.h f10, f11, f12, f13
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# CHECK-INST: fmsub.h fa4, fa5, fa6, fa7, dyn
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# CHECK-ALIAS: fmsub.h fa4, fa5, fa6, fa7{{[[:space:]]}}
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fmsub.h f14, f15, f16, f17
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# CHECK-INST: fnmsub.h fs2, fs3, fs4, fs5, dyn
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# CHECK-ALIAS: fnmsub.h fs2, fs3, fs4, fs5{{[[:space:]]}}
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fnmsub.h f18, f19, f20, f21
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# CHECK-INST: fnmadd.h fs6, fs7, fs8, fs9, dyn
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# CHECK-ALIAS: fnmadd.h fs6, fs7, fs8, fs9{{[[:space:]]}}
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fnmadd.h f22, f23, f24, f25
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# CHECK-INST: fadd.h fs10, fs11, ft8, dyn
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# CHECK-ALIAS: fadd.h fs10, fs11, ft8{{[[:space:]]}}
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fadd.h f26, f27, f28
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# CHECK-INST: fsub.h ft9, ft10, ft11, dyn
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# CHECK-ALIAS: fsub.h ft9, ft10, ft11{{[[:space:]]}}
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fsub.h f29, f30, f31
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# CHECK-INST: fmul.h ft0, ft1, ft2, dyn
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# CHECK-ALIAS: fmul.h ft0, ft1, ft2{{[[:space:]]}}
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fmul.h ft0, ft1, ft2
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# CHECK-INST: fdiv.h ft3, ft4, ft5, dyn
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# CHECK-ALIAS: fdiv.h ft3, ft4, ft5{{[[:space:]]}}
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fdiv.h ft3, ft4, ft5
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# CHECK-INST: fsqrt.h ft6, ft7, dyn
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# CHECK-ALIAS: fsqrt.h ft6, ft7{{[[:space:]]}}
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fsqrt.h ft6, ft7
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# CHECK-INST: fcvt.w.h a0, fs5, dyn
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# CHECK-ALIAS: fcvt.w.h a0, fs5{{[[:space:]]}}
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fcvt.w.h a0, fs5
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# CHECK-INST: fcvt.wu.h a1, fs6, dyn
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# CHECK-ALIAS: fcvt.wu.h a1, fs6{{[[:space:]]}}
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fcvt.wu.h a1, fs6
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# CHECK-INST: fcvt.h.w ft11, a4, dyn
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# CHECK-ALIAS: fcvt.h.w ft11, a4{{[[:space:]]}}
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fcvt.h.w ft11, a4
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# CHECK-INST: fcvt.h.wu ft0, a5, dyn
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# CHECK-ALIAS: fcvt.h.wu ft0, a5{{[[:space:]]}}
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fcvt.h.wu ft0, a5
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