218 lines
8.7 KiB
ArmAsm
218 lines
8.7 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate out of upper bound [-8, 7].
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st1h z29.h, p5, [x7, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1h z29.h, p5, [x7, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z29.h, p5, [x4, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1h z29.h, p5, [x4, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z21.s, p2, [x1, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1h z21.s, p2, [x1, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z17.s, p5, [x1, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1h z17.s, p5, [x1, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.d, p1, [x14, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1h z0.d, p1, [x14, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z24.d, p3, [x16, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: st1h z24.d, p3, [x16, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate
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st1h z15.h, p8, [x0, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st1h z15.h, p8, [x0, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z17.s, p8, [x20, #2, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st1h z17.s, p8, [x20, #2, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z15.d, p8, [x0, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st1h z15.d, p8, [x0, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z15.d, p7.b, [x0, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st1h z15.d, p7.b, [x0, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z15.d, p7.b, [x0, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: st1h z15.d, p7.b, [x0, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list
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st1h { }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: st1h { }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h { z1.h, z2.h }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st1h { z1.h, z2.h }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h { v0.8h }, p0, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st1h { v0.8h }, p0, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st1h z0.h, p0, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st1h z0.h, p0, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.h, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st1h z0.h, p0, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.h, p0, [x0, x0, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st1h z0.h, p0, [x0, x0, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.h, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st1h z0.h, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.h, p0, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st1h z0.h, p0, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + vector addressing modes
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st1h z0.d, p0, [x0, z0.h]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st1h z0.d, p0, [x0, z0.h]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.d, p0, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: st1h z0.d, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.s, p0, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
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// CHECK-NEXT: st1h z0.s, p0, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.s, p0, [x0, z0.s, uxtw #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
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// CHECK-NEXT: st1h z0.s, p0, [x0, z0.s, uxtw #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.s, p0, [x0, z0.s, lsl #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
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// CHECK-NEXT: st1h z0.s, p0, [x0, z0.s, lsl #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.d, p0, [x0, z0.d, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
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// CHECK-NEXT: st1h z0.d, p0, [x0, z0.d, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.d, p0, [x0, z0.d, sxtw #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
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// CHECK-NEXT: st1h z0.d, p0, [x0, z0.d, sxtw #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector + immediate addressing modes
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st1h z0.s, p0, [z0.s, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.s, p0, [z0.s, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.s, p0, [z0.s, #-2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.s, p0, [z0.s, #-2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.s, p0, [z0.s, #63]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.s, p0, [z0.s, #63]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.s, p0, [z0.s, #64]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.s, p0, [z0.s, #64]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.s, p0, [z0.s, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.s, p0, [z0.s, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.d, p0, [z0.d, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.d, p0, [z0.d, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.d, p0, [z0.d, #-2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.d, p0, [z0.d, #-2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.d, p0, [z0.d, #63]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.d, p0, [z0.d, #63]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.d, p0, [z0.d, #64]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.d, p0, [z0.d, #64]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st1h z0.d, p0, [z0.d, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: st1h z0.d, p0, [z0.d, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p7/z, z6.d
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st1h { z31.d }, p7, [z31.d, #62]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st1h { z31.d }, p7, [z31.d, #62]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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st1h { z31.d }, p7, [z31.d, #62]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: st1h { z31.d }, p7, [z31.d, #62]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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