104 lines
3.4 KiB
ArmAsm
104 lines
3.4 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid result register
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sqincw w0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincw w0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincw wsp
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincw wsp
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincw sp
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincw sp
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincw z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sqincw z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Operands not matching up
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sqincw x0, w1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
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// CHECK-NEXT: sqincw x0, w1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincw x0, x0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincw x0, x0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Immediate not compatible with encode/decode function.
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sqincw x0, all, mul #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
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// CHECK-NEXT: sqincw x0, all, mul #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincw x0, all, mul #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
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// CHECK-NEXT: sqincw x0, all, mul #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincw x0, all, mul #17
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
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// CHECK-NEXT: sqincw x0, all, mul #17
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate patterns
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sqincw x0, vl512
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincw x0, vl512
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincw x0, vl9
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincw x0, vl9
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincw x0, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
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// CHECK-NEXT: sqincw x0, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincw x0, #32
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
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// CHECK-NEXT: sqincw x0, #32
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.s, p0/z, z7.s
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sqincw z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: sqincw z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0.s, p0/z, z7.s
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sqincw z0.s, pow2, mul #16
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: sqincw z0.s, pow2, mul #16
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0.s, p0/z, z7.s
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sqincw z0.s, pow2
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: sqincw z0.s, pow2
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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