75 lines
2.7 KiB
ArmAsm
75 lines
2.7 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid element size
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sdot z0.s, z1.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sdot z0.s, z1.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sdot z0.d, z1.b, z31.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sdot z0.d, z1.b, z31.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sdot z0.d, z1.s, z31.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sdot z0.d, z1.s, z31.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid restricted register for indexed vector.
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sdot z0.s, z1.b, z8.b[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: sdot z0.s, z1.b, z8.b[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sdot z0.d, z1.h, z16.h[1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: sdot z0.d, z1.h, z16.h[1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element index
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sdot z0.s, z1.b, z7.b[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: sdot z0.s, z1.b, z7.b[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sdot z0.s, z1.b, z7.b[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: sdot z0.s, z1.b, z7.b[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sdot z0.d, z1.h, z15.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
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// CHECK-NEXT: sdot z0.d, z1.h, z15.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sdot z0.d, z1.h, z15.h[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
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// CHECK-NEXT: sdot z0.d, z1.h, z15.h[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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sdot z0.d, z1.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: sdot z0.d, z1.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0.d, p0/z, z7.d
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sdot z0.d, z1.h, z15.h[1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: sdot z0.d, z1.h, z15.h[1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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