98 lines
3.9 KiB
ArmAsm
98 lines
3.9 KiB
ArmAsm
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// This test file is mostly empty because most 'movprfx' tests are embedded
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// with other instructions that are destructive and can be prefixed
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// by the movprfx instruction. A list of destructive instructions
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// is given below by their mnemonic, which have tests in corresponding
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// <mnemonic>.s test files:
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//
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// abs decp fdivr fnmla fsubr mov sdivr sqincw umulh
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// add eon fmad fnmls ftmad msb sdot sqsub uqadd
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// and eor fmax fnmsb incd mul smax sub uqdecd
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// asr ext fmaxnm frecpx inch neg smin subr uqdech
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// asrd fabd fmin frinta incp not smulh sxtb uqdecp
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// asrr fabs fminnm frinti incw orn splice sxth uqdecw
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// bic fadd fmla frintm insr orr sqadd sxtw uqincd
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// clasta fcadd fmls frintn lsl rbit sqdecd uabd uqinch
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// clastb fcmla fmov frintp lslr revb sqdech ucvtf uqincp
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// cls fcpy fmsb frintx lsr revh sqdecp udiv uqincw
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// clz fcvt fmul frintz lsrr revw sqdecw udivr uqsub
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// cnot fcvtzs fmulx fscale mad sabd sqincd udot uxtb
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// cnt fcvtzu fneg fsqrt mla scvtf sqinch umax uxth
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// cpy fdiv fnmad fsub mls sdiv sqincp umin uxtw
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// ------------------------------------------------------------------------- //
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// Test compatibility with MOVPRFX instruction with BRK and HLT.
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//
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// Section 7.1.2 of the SVE Architecture Reference Manual Supplement:
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// "it is permitted to use MOVPRFX to prefix an A64 BRK or HLT instruction"
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movprfx z0, z1
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// CHECK-INST: movprfx z0, z1
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// CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 bc 20 04 <unknown>
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hlt #1
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// CHECK-INST: hlt #0x1
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// CHECK-ENCODING: [0x20,0x00,0x40,0xd4]
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movprfx z0.d, p0/z, z1.d
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// CHECK-INST: movprfx z0.d, p0/z, z1.d
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// CHECK-ENCODING: [0x20,0x20,0xd0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 20 d0 04 <unknown>
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hlt #1
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// CHECK-INST: hlt #0x1
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// CHECK-ENCODING: [0x20,0x00,0x40,0xd4]
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movprfx z0, z1
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// CHECK-INST: movprfx z0, z1
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// CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 bc 20 04 <unknown>
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brk #1
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// CHECK-INST: brk #0x1
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// CHECK-ENCODING: [0x20,0x00,0x20,0xd4]
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movprfx z0.d, p0/z, z1.d
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// CHECK-INST: movprfx z0.d, p0/z, z1.d
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// CHECK-ENCODING: [0x20,0x20,0xd0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 20 d0 04 <unknown>
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brk #1
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// CHECK-INST: brk #0x1
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// CHECK-ENCODING: [0x20,0x00,0x20,0xd4]
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// ------------------------------------------------------------------------- //
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// Ensure we don't try to apply a prefix to subsequent instructions (upon success)
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movprfx z0, z1
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// CHECK-INST: movprfx z0, z1
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// CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 bc 20 04 <unknown>
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add z0.d, p0/m, z0.d, z1.d
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// CHECK-INST: add z0.d, p0/m, z0.d, z1.d
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// CHECK-ENCODING: [0x20,0x00,0xc0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 00 c0 04 <unknown>
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add z0.d, p0/m, z0.d, z1.d
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// CHECK-INST: add z0.d, p0/m, z0.d, z1.d
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// CHECK-ENCODING: [0x20,0x00,0xc0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 00 c0 04 <unknown>
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