87 lines
4.2 KiB
ArmAsm
87 lines
4.2 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+f32mm,+f64mm 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// FMMLA (SVE)
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// Invalid element size
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fmmla z0.h, z1.h, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// Mis-matched element size
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fmmla z0.d, z1.s, z2.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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fmmla z0.s, z1.d, z2.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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fmmla z0.s, z1.s, z2.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// --------------------------------------------------------------------------//
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// LD1RO (SVE, scalar plus immediate)
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// Immediate too high (>224)
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ld1rob { z0.b }, p1/z, [x2, #256]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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ld1roh { z0.h }, p1/z, [x2, #256]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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ld1row { z0.s }, p1/z, [x2, #256]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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ld1rod { z0.d }, p1/z, [x2, #256]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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// Immediate too low (<-256)
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ld1rob { z0.b }, p1/z, [x2, #-288]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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ld1roh { z0.h }, p1/z, [x2, #-288]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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ld1row { z0.s }, p1/z, [x2, #-288]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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ld1rod { z0.d }, p1/z, [x2, #-288]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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// Immediate not a multiple of 32
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ld1rob { z0.b }, p1/z, [x2, #16]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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ld1roh { z0.h }, p1/z, [x2, #16]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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ld1row { z0.s }, p1/z, [x2, #16]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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ld1rod { z0.d }, p1/z, [x2, #16]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 32 in range [-256, 224].
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// Prediate register too high
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ld1rob { z0.b }, p8/z, [x2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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ld1roh { z0.h }, p8/z, [x2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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ld1row { z0.s }, p8/z, [x2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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ld1rod { z0.d }, p8/z, [x2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// --------------------------------------------------------------------------//
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// LD1RO (SVE, scalar plus scalar)
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// Shift amount not matched to data width
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ld1rob { z0.b }, p1/z, [x2, x3, lsl #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
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ld1roh { z0.h }, p1/z, [x2, x3, lsl #0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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ld1row { z0.s }, p1/z, [x2, x3, lsl #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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ld1rod { z0.d }, p1/z, [x2, x3, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// Prediate register too high
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ld1rob { z0.b }, p8/z, [x2, x3, lsl #0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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ld1roh { z0.h }, p8/z, [x2, x3, lsl #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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ld1row { z0.s }, p8/z, [x2, x3, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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ld1rod { z0.d }, p8/z, [x2, x3, lsl #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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