49 lines
1.9 KiB
ArmAsm
49 lines
1.9 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid immediate (in range [0, 63]).
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ld1rsb z0.h, p1/z, [x0, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
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// CHECK-NEXT: ld1rsb z0.h, p1/z, [x0, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1rsb z0.h, p1/z, [x0, #64]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be in range [0, 63].
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// CHECK-NEXT: ld1rsb z0.h, p1/z, [x0, #64]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid result vector element size
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ld1rsb z0.b, p1/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1rsb z0.b, p1/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// restricted predicate has range [0, 7].
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ld1rsb z0.h, p8/z, [x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ld1rsb z0.h, p8/z, [x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31.d, p7/z, z6.d
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ld1rsb { z31.d }, p7/z, [sp, #63]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31, z6
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ld1rsb { z31.d }, p7/z, [sp, #63]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1rsb { z31.d }, p7/z, [sp, #63]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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