133 lines
3.1 KiB
LLVM
133 lines
3.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+tbm | FileCheck %s --check-prefix=X64
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; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/tbm-builtins.c
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define i64 @test__bextri_u64(i64 %a0) {
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; X64-LABEL: test__bextri_u64:
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; X64: # %bb.0:
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; X64-NEXT: bextrq $3841, %rdi, %rax # imm = 0xF01
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; X64-NEXT: retq
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%1 = call i64 @llvm.x86.tbm.bextri.u64(i64 %a0, i64 3841)
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ret i64 %1
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}
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define i64 @test__blcfill_u64(i64 %a0) {
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; X64-LABEL: test__blcfill_u64:
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; X64: # %bb.0:
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; X64-NEXT: leaq 1(%rdi), %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%1 = add i64 %a0, 1
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%2 = and i64 %a0, %1
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ret i64 %2
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}
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define i64 @test__blci_u64(i64 %a0) {
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; X64-LABEL: test__blci_u64:
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; X64: # %bb.0:
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; X64-NEXT: leaq 1(%rdi), %rax
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; X64-NEXT: xorq $-1, %rax
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; X64-NEXT: orq %rdi, %rax
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; X64-NEXT: retq
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%1 = add i64 %a0, 1
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%2 = xor i64 %1, -1
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%3 = or i64 %a0, %2
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ret i64 %3
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}
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define i64 @test__blcic_u64(i64 %a0) {
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; X64-LABEL: test__blcic_u64:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movq %rdi, %rcx
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; X64-NEXT: xorq $-1, %rcx
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; X64-NEXT: addq $1, %rax
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; X64-NEXT: andq %rcx, %rax
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; X64-NEXT: retq
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%1 = xor i64 %a0, -1
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%2 = add i64 %a0, 1
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%3 = and i64 %1, %2
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ret i64 %3
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}
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define i64 @test__blcmsk_u64(i64 %a0) {
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; X64-LABEL: test__blcmsk_u64:
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; X64: # %bb.0:
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; X64-NEXT: leaq 1(%rdi), %rax
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; X64-NEXT: xorq %rdi, %rax
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; X64-NEXT: retq
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%1 = add i64 %a0, 1
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%2 = xor i64 %a0, %1
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ret i64 %2
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}
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define i64 @test__blcs_u64(i64 %a0) {
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; X64-LABEL: test__blcs_u64:
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; X64: # %bb.0:
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; X64-NEXT: leaq 1(%rdi), %rax
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; X64-NEXT: orq %rdi, %rax
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; X64-NEXT: retq
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%1 = add i64 %a0, 1
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%2 = or i64 %a0, %1
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ret i64 %2
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}
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define i64 @test__blsfill_u64(i64 %a0) {
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; X64-LABEL: test__blsfill_u64:
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; X64: # %bb.0:
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; X64-NEXT: leaq -1(%rdi), %rax
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; X64-NEXT: orq %rdi, %rax
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; X64-NEXT: retq
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%1 = sub i64 %a0, 1
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%2 = or i64 %a0, %1
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ret i64 %2
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}
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define i64 @test__blsic_u64(i64 %a0) {
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; X64-LABEL: test__blsic_u64:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movq %rdi, %rcx
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; X64-NEXT: xorq $-1, %rcx
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: orq %rcx, %rax
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; X64-NEXT: retq
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%1 = xor i64 %a0, -1
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%2 = sub i64 %a0, 1
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%3 = or i64 %1, %2
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ret i64 %3
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}
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define i64 @test__t1mskc_u64(i64 %a0) {
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; X64-LABEL: test__t1mskc_u64:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movq %rdi, %rcx
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; X64-NEXT: xorq $-1, %rcx
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; X64-NEXT: addq $1, %rax
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; X64-NEXT: orq %rcx, %rax
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; X64-NEXT: retq
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%1 = xor i64 %a0, -1
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%2 = add i64 %a0, 1
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%3 = or i64 %1, %2
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ret i64 %3
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}
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define i64 @test__tzmsk_u64(i64 %a0) {
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; X64-LABEL: test__tzmsk_u64:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movq %rdi, %rcx
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; X64-NEXT: xorq $-1, %rcx
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; X64-NEXT: subq $1, %rax
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; X64-NEXT: andq %rcx, %rax
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; X64-NEXT: retq
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%1 = xor i64 %a0, -1
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%2 = sub i64 %a0, 1
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%3 = and i64 %1, %2
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ret i64 %3
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}
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declare i64 @llvm.x86.tbm.bextri.u64(i64, i64)
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