llvm-for-llvmta/test/CodeGen/X86/pr43509.ll

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2022-04-25 10:02:23 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s
define <8 x i8> @foo(<8 x float> %arg) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: vcmpgtps {{.*}}(%rip){1to8}, %ymm0, %k0
; CHECK-NEXT: vpmovm2b %k0, %xmm1
; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vcmpltps %ymm2, %ymm0, %k1
; CHECK-NEXT: vmovdqu8 {{.*}}(%rip), %xmm0 {%k1} {z}
; CHECK-NEXT: vpand %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
bb:
%tmp = xor <8 x i8> zeroinitializer, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
%tmp1 = fcmp reassoc nsz contract ogt <8 x float> %arg, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
%tmp2 = zext <8 x i1> %tmp1 to <8 x i8>
%tmp3 = and <8 x i8> %tmp, %tmp2
%tmp4 = fcmp reassoc nsz contract ogt <8 x float> zeroinitializer, %arg
%tmp5 = or <8 x i1> zeroinitializer, %tmp4
%tmp6 = zext <8 x i1> %tmp5 to <8 x i8>
%tmp7 = and <8 x i8> %tmp3, %tmp6
ret <8 x i8> %tmp7
}