114 lines
3.3 KiB
LLVM
114 lines
3.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck %s
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define i64 @t0(x86_mmx* %p) {
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; CHECK-LABEL: t0:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: paddq %mm0, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t = load x86_mmx, x86_mmx* %p
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%u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %t)
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%s = bitcast x86_mmx %u to i64
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ret i64 %s
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}
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define i64 @t1(x86_mmx* %p) {
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; CHECK-LABEL: t1:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: paddd %mm0, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t = load x86_mmx, x86_mmx* %p
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%u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %t)
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%s = bitcast x86_mmx %u to i64
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ret i64 %s
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}
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define i64 @t2(x86_mmx* %p) {
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; CHECK-LABEL: t2:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: paddw %mm0, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t = load x86_mmx, x86_mmx* %p
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%u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %t)
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%s = bitcast x86_mmx %u to i64
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ret i64 %s
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}
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define i64 @t3(x86_mmx* %p) {
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; CHECK-LABEL: t3:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: paddb %mm0, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t = load x86_mmx, x86_mmx* %p
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%u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %t)
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%s = bitcast x86_mmx %u to i64
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ret i64 %s
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}
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@R = external global x86_mmx
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define void @t4(<1 x i64> %A, <1 x i64> %B) {
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; CHECK-LABEL: t4:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: movq %rdi, %mm0
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; CHECK-NEXT: movq %rsi, %mm1
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; CHECK-NEXT: paddusw %mm0, %mm1
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; CHECK-NEXT: movq _R@{{.*}}(%rip), %rax
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; CHECK-NEXT: movq %mm1, (%rax)
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%tmp2 = bitcast <1 x i64> %A to x86_mmx
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%tmp3 = bitcast <1 x i64> %B to x86_mmx
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%tmp7 = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %tmp2, x86_mmx %tmp3)
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store x86_mmx %tmp7, x86_mmx* @R
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tail call void @llvm.x86.mmx.emms()
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ret void
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}
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define i64 @t5(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: t5:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movd %esi, %xmm0
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; CHECK-NEXT: movd %edi, %xmm1
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; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; CHECK-NEXT: movq %xmm1, %rax
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; CHECK-NEXT: retq
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%v0 = insertelement <2 x i32> undef, i32 %a, i32 0
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%v1 = insertelement <2 x i32> %v0, i32 %b, i32 1
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%conv = bitcast <2 x i32> %v1 to i64
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ret i64 %conv
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}
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declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
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define <1 x i64> @t6(i64 %t) {
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; CHECK-LABEL: t6:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq %rdi, %mm0
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; CHECK-NEXT: psllq $48, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t1 = insertelement <1 x i64> undef, i64 %t, i32 0
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%t0 = bitcast <1 x i64> %t1 to x86_mmx
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%t2 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %t0, i32 48)
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%t3 = bitcast x86_mmx %t2 to <1 x i64>
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ret <1 x i64> %t3
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}
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declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
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declare void @llvm.x86.mmx.emms()
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