189 lines
6.4 KiB
LLVM
189 lines
6.4 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefixes=X86,X86-NOSSE
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; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
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; RUN: llc < %s -mtriple=i686-unknown -mattr=avx | FileCheck %s --check-prefixes=X86,X86-AVX
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; RUN: llc < %s -mtriple=i686-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X86,X86-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64,X64-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64-AVX
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define i64 @testmsxs(float %x) {
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; X86-NOSSE-LABEL: testmsxs:
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; X86-NOSSE: # %bb.0: # %entry
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; X86-NOSSE-NEXT: pushl %ebp
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; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
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; X86-NOSSE-NEXT: .cfi_offset %ebp, -8
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; X86-NOSSE-NEXT: movl %esp, %ebp
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; X86-NOSSE-NEXT: .cfi_def_cfa_register %ebp
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; X86-NOSSE-NEXT: andl $-8, %esp
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; X86-NOSSE-NEXT: subl $8, %esp
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; X86-NOSSE-NEXT: flds 8(%ebp)
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; X86-NOSSE-NEXT: fistpll (%esp)
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; X86-NOSSE-NEXT: movl (%esp), %eax
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NOSSE-NEXT: movl %ebp, %esp
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; X86-NOSSE-NEXT: popl %ebp
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; X86-NOSSE-NEXT: .cfi_def_cfa %esp, 4
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; X86-NOSSE-NEXT: retl
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;
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; X86-SSE2-LABEL: testmsxs:
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; X86-SSE2: # %bb.0: # %entry
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; X86-SSE2-NEXT: pushl %ebp
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; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
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; X86-SSE2-NEXT: .cfi_offset %ebp, -8
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; X86-SSE2-NEXT: movl %esp, %ebp
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; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
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; X86-SSE2-NEXT: andl $-8, %esp
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; X86-SSE2-NEXT: subl $8, %esp
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; X86-SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-SSE2-NEXT: movss %xmm0, (%esp)
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; X86-SSE2-NEXT: flds (%esp)
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; X86-SSE2-NEXT: fistpll (%esp)
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; X86-SSE2-NEXT: movl (%esp), %eax
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-SSE2-NEXT: movl %ebp, %esp
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; X86-SSE2-NEXT: popl %ebp
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; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
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; X86-SSE2-NEXT: retl
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;
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; X86-AVX-LABEL: testmsxs:
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; X86-AVX: # %bb.0: # %entry
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; X86-AVX-NEXT: pushl %ebp
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; X86-AVX-NEXT: .cfi_def_cfa_offset 8
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; X86-AVX-NEXT: .cfi_offset %ebp, -8
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; X86-AVX-NEXT: movl %esp, %ebp
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; X86-AVX-NEXT: .cfi_def_cfa_register %ebp
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; X86-AVX-NEXT: andl $-8, %esp
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; X86-AVX-NEXT: subl $8, %esp
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; X86-AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-AVX-NEXT: vmovss %xmm0, (%esp)
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; X86-AVX-NEXT: flds (%esp)
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; X86-AVX-NEXT: fistpll (%esp)
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; X86-AVX-NEXT: movl (%esp), %eax
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-AVX-NEXT: movl %ebp, %esp
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; X86-AVX-NEXT: popl %ebp
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; X86-AVX-NEXT: .cfi_def_cfa %esp, 4
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; X86-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: testmsxs:
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; X64-SSE: # %bb.0: # %entry
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; X64-SSE-NEXT: cvtss2si %xmm0, %rax
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: testmsxs:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: vcvtss2si %xmm0, %rax
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; X64-AVX-NEXT: retq
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entry:
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%0 = tail call i64 @llvm.llrint.f32(float %x)
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ret i64 %0
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}
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define i64 @testmsxd(double %x) {
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; X86-NOSSE-LABEL: testmsxd:
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; X86-NOSSE: # %bb.0: # %entry
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; X86-NOSSE-NEXT: pushl %ebp
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; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
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; X86-NOSSE-NEXT: .cfi_offset %ebp, -8
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; X86-NOSSE-NEXT: movl %esp, %ebp
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; X86-NOSSE-NEXT: .cfi_def_cfa_register %ebp
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; X86-NOSSE-NEXT: andl $-8, %esp
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; X86-NOSSE-NEXT: subl $8, %esp
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; X86-NOSSE-NEXT: fldl 8(%ebp)
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; X86-NOSSE-NEXT: fistpll (%esp)
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; X86-NOSSE-NEXT: movl (%esp), %eax
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NOSSE-NEXT: movl %ebp, %esp
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; X86-NOSSE-NEXT: popl %ebp
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; X86-NOSSE-NEXT: .cfi_def_cfa %esp, 4
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; X86-NOSSE-NEXT: retl
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;
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; X86-SSE2-LABEL: testmsxd:
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; X86-SSE2: # %bb.0: # %entry
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; X86-SSE2-NEXT: pushl %ebp
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; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
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; X86-SSE2-NEXT: .cfi_offset %ebp, -8
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; X86-SSE2-NEXT: movl %esp, %ebp
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; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
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; X86-SSE2-NEXT: andl $-8, %esp
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; X86-SSE2-NEXT: subl $8, %esp
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; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-SSE2-NEXT: movsd %xmm0, (%esp)
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; X86-SSE2-NEXT: fldl (%esp)
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; X86-SSE2-NEXT: fistpll (%esp)
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; X86-SSE2-NEXT: movl (%esp), %eax
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-SSE2-NEXT: movl %ebp, %esp
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; X86-SSE2-NEXT: popl %ebp
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; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
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; X86-SSE2-NEXT: retl
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;
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; X86-AVX-LABEL: testmsxd:
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; X86-AVX: # %bb.0: # %entry
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; X86-AVX-NEXT: pushl %ebp
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; X86-AVX-NEXT: .cfi_def_cfa_offset 8
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; X86-AVX-NEXT: .cfi_offset %ebp, -8
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; X86-AVX-NEXT: movl %esp, %ebp
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; X86-AVX-NEXT: .cfi_def_cfa_register %ebp
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; X86-AVX-NEXT: andl $-8, %esp
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; X86-AVX-NEXT: subl $8, %esp
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; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; X86-AVX-NEXT: vmovsd %xmm0, (%esp)
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; X86-AVX-NEXT: fldl (%esp)
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; X86-AVX-NEXT: fistpll (%esp)
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; X86-AVX-NEXT: movl (%esp), %eax
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-AVX-NEXT: movl %ebp, %esp
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; X86-AVX-NEXT: popl %ebp
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; X86-AVX-NEXT: .cfi_def_cfa %esp, 4
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; X86-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: testmsxd:
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; X64-SSE: # %bb.0: # %entry
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; X64-SSE-NEXT: cvtsd2si %xmm0, %rax
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: testmsxd:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: vcvtsd2si %xmm0, %rax
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; X64-AVX-NEXT: retq
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entry:
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%0 = tail call i64 @llvm.llrint.f64(double %x)
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ret i64 %0
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}
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define i64 @testmsll(x86_fp80 %x) {
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; X86-LABEL: testmsll:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %ebp
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: .cfi_offset %ebp, -8
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: .cfi_def_cfa_register %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: fldt 8(%ebp)
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; X86-NEXT: fistpll (%esp)
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; X86-NEXT: movl (%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: .cfi_def_cfa %esp, 4
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; X86-NEXT: retl
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;
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; X64-LABEL: testmsll:
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; X64: # %bb.0: # %entry
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; X64-NEXT: fldt {{[0-9]+}}(%rsp)
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; X64-NEXT: fistpll -{{[0-9]+}}(%rsp)
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; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; X64-NEXT: retq
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entry:
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%0 = tail call i64 @llvm.llrint.f80(x86_fp80 %x)
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ret i64 %0
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}
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declare i64 @llvm.llrint.f32(float) nounwind readnone
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declare i64 @llvm.llrint.f64(double) nounwind readnone
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declare i64 @llvm.llrint.f80(x86_fp80) nounwind readnone
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