119 lines
3.5 KiB
LLVM
119 lines
3.5 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mtriple=x86_64-unknown-unknown -x86-indirect-branch-tracking | FileCheck %s
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; This test is for CET enhancement.
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;
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; ENDBR32 and ENDBR64 have specific opcodes:
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; ENDBR32: F3 0F 1E FB
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; ENDBR64: F3 0F 1E FA
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; And we want that attackers won’t find unintended ENDBR32/64
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; opcode matches in the binary
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; Here’s an example:
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; If the compiler had to generate asm for the following code:
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; a = 0xF30F1EFA
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; it could, for example, generate:
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; mov 0xF30F1EFA, dword ptr[a]
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; In such a case, the binary would include a gadget that starts
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; with a fake ENDBR64 opcode. Therefore, we split such generation
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; into multiple operations, let it not shows in the binary.
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; 0xF30F1EFA == -217112838 ~0xF30F1EFA == 217112837 (0xCF0E105)
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; 0x000123F32E0F1EFA == 321002333478650
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; ~0x000123F32E0F1EFA == -321002333478651 (0XFFFEDC0CD1F0E105)
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; test for MOV64ri
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define dso_local i64 @foo(i64* %azx) #0 {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: endbr64
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; CHECK-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movabsq $-321002333478651, %rax # imm = 0xFFFEDC0CD1F0E105
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; CHECK-NEXT: notq %rax
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; CHECK-NEXT: andq %rax, (%rdi)
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: movq (%rax), %rax
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; CHECK-NEXT: retq
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entry:
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%azx.addr = alloca i64*, align 8
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store i64* %azx, i64** %azx.addr, align 8
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%0 = load i64*, i64** %azx.addr, align 8
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%1 = load i64, i64* %0, align 8
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%and = and i64 %1, 321002333478650
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%2 = load i64*, i64** %azx.addr, align 8
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store i64 %and, i64* %2, align 8
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%3 = load i64*, i64** %azx.addr, align 8
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%4 = load i64, i64* %3, align 8
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ret i64 %4
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}
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@bzx = dso_local local_unnamed_addr global i32 -217112837, align 4
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; test for AND32ri
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define dso_local i32 @foo2() local_unnamed_addr #0 {
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; CHECK-LABEL: foo2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: endbr64
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; CHECK-NEXT: movl {{.*}}(%rip), %ecx
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; CHECK-NEXT: addl %ecx, %ecx
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; CHECK-NEXT: movl $217112837, %eax # imm = 0xCF0E105
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; CHECK-NEXT: notl %eax
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; CHECK-NEXT: andl %ecx, %eax
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; CHECK-NEXT: retq
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entry:
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%0 = load i32, i32* @bzx, align 4
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%mul = shl nsw i32 %0, 1
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%and = and i32 %mul, -217112838
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ret i32 %and
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}
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@czx = dso_local global i32 -217112837, align 4
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; test for AND32mi
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define dso_local nonnull i32* @foo3() local_unnamed_addr #0 {
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; CHECK-LABEL: foo3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: endbr64
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; CHECK-NEXT: movl $217112837, %eax # imm = 0xCF0E105
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; CHECK-NEXT: notl %eax
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; CHECK-NEXT: andl %eax, {{.*}}(%rip)
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; CHECK-NEXT: movl $czx, %eax
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; CHECK-NEXT: retq
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entry:
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%0 = load i32, i32* @czx, align 4
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%and = and i32 %0, -217112838
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store i32 %and, i32* @czx, align 4
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ret i32* @czx
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}
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; test for MOV32mi
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define dso_local i32 @foo4() #0 {
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; CHECK-LABEL: foo4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: endbr64
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; CHECK-NEXT: movl $217112837, %eax # imm = 0xCF0E105
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; CHECK-NEXT: notl %eax
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; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: retq
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entry:
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%dzx = alloca i32, align 4
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store i32 -217112838, i32* %dzx, align 4
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%0 = load i32, i32* %dzx, align 4
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ret i32 %0
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}
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define dso_local i64 @foo5() #0 {
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; CHECK-LABEL: foo5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: endbr64
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; CHECK-NEXT: movabsq $-4077854459, %rax # imm = 0xFFFFFFFF0CF0E105
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; CHECK-NEXT: notq %rax
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; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: retq
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entry:
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%ezx = alloca i64, align 8
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store i64 4077854458, i64* %ezx, align 8
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%0 = load i64, i64* %ezx, align 8
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ret i64 %0
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}
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