162 lines
4.7 KiB
LLVM
162 lines
4.7 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1,-avx,+rdrnd,+rdseed | FileCheck %s
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define i32 @foo(<2 x i64> %c, i32 %a, i32 %b) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: ptest %xmm0, %xmm0
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; CHECK-NEXT: cmovnel %esi, %eax
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; CHECK-NEXT: retq
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%t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)
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%t2 = icmp ne i32 %t1, 0
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%t3 = select i1 %t2, i32 %a, i32 %b
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ret i32 %t3
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}
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define i32 @bar(<2 x i64> %c) {
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; CHECK-LABEL: bar:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ptest %xmm0, %xmm0
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; CHECK-NEXT: jne .LBB1_2
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; CHECK-NEXT: # %bb.1: # %if-true-block
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB1_2: # %endif-block
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retq
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entry:
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%0 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)
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%1 = icmp ne i32 %0, 0
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block:
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ret i32 0
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endif-block:
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ret i32 1
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}
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define i32 @bax(<2 x i64> %c) {
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; CHECK-LABEL: bax:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: ptest %xmm0, %xmm0
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)
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%t2 = icmp eq i32 %t1, 1
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%t3 = zext i1 %t2 to i32
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ret i32 %t3
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}
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define i16 @rnd16(i16 %arg) nounwind {
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; CHECK-LABEL: rnd16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: rdrandw %cx
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: addl %ecx, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%1 = tail call { i16, i32 } @llvm.x86.rdrand.16() nounwind
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%2 = extractvalue { i16, i32 } %1, 0
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%3 = extractvalue { i16, i32 } %1, 1
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%4 = icmp eq i32 %3, 0
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%5 = select i1 %4, i16 0, i16 %arg
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%6 = add i16 %5, %2
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ret i16 %6
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}
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define i32 @rnd32(i32 %arg) nounwind {
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; CHECK-LABEL: rnd32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: rdrandl %ecx
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: addl %ecx, %eax
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; CHECK-NEXT: retq
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%1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
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%2 = extractvalue { i32, i32 } %1, 0
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%3 = extractvalue { i32, i32 } %1, 1
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%4 = icmp eq i32 %3, 0
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%5 = select i1 %4, i32 0, i32 %arg
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%6 = add i32 %5, %2
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ret i32 %6
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}
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define i64 @rnd64(i64 %arg) nounwind {
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; CHECK-LABEL: rnd64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: rdrandq %rcx
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; CHECK-NEXT: cmovbq %rdi, %rax
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; CHECK-NEXT: addq %rcx, %rax
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; CHECK-NEXT: retq
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%1 = tail call { i64, i32 } @llvm.x86.rdrand.64() nounwind
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%2 = extractvalue { i64, i32 } %1, 0
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%3 = extractvalue { i64, i32 } %1, 1
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%4 = icmp eq i32 %3, 0
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%5 = select i1 %4, i64 0, i64 %arg
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%6 = add i64 %5, %2
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ret i64 %6
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}
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define i16 @seed16(i16 %arg) nounwind {
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; CHECK-LABEL: seed16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: rdseedw %cx
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: addl %ecx, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%1 = tail call { i16, i32 } @llvm.x86.rdseed.16() nounwind
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%2 = extractvalue { i16, i32 } %1, 0
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%3 = extractvalue { i16, i32 } %1, 1
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%4 = icmp eq i32 %3, 0
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%5 = select i1 %4, i16 0, i16 %arg
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%6 = add i16 %5, %2
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ret i16 %6
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}
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define i32 @seed32(i32 %arg) nounwind {
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; CHECK-LABEL: seed32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: rdseedl %ecx
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: addl %ecx, %eax
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; CHECK-NEXT: retq
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%1 = tail call { i32, i32 } @llvm.x86.rdseed.32() nounwind
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%2 = extractvalue { i32, i32 } %1, 0
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%3 = extractvalue { i32, i32 } %1, 1
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%4 = icmp eq i32 %3, 0
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%5 = select i1 %4, i32 0, i32 %arg
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%6 = add i32 %5, %2
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ret i32 %6
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}
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define i64 @seed64(i64 %arg) nounwind {
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; CHECK-LABEL: seed64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: rdseedq %rcx
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; CHECK-NEXT: cmovbq %rdi, %rax
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; CHECK-NEXT: addq %rcx, %rax
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; CHECK-NEXT: retq
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%1 = tail call { i64, i32 } @llvm.x86.rdseed.64() nounwind
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%2 = extractvalue { i64, i32 } %1, 0
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%3 = extractvalue { i64, i32 } %1, 1
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%4 = icmp eq i32 %3, 0
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%5 = select i1 %4, i64 0, i64 %arg
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%6 = add i64 %5, %2
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ret i64 %6
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}
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declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
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declare { i16, i32 } @llvm.x86.rdrand.16() nounwind
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declare { i32, i32 } @llvm.x86.rdrand.32() nounwind
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declare { i64, i32 } @llvm.x86.rdrand.64() nounwind
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declare { i16, i32 } @llvm.x86.rdseed.16() nounwind
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declare { i32, i32 } @llvm.x86.rdseed.32() nounwind
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declare { i64, i32 } @llvm.x86.rdseed.64() nounwind
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