92 lines
3.6 KiB
LLVM
92 lines
3.6 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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define arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vminnmq_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vminnm.f16 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call <8 x half> @llvm.minnum.v8f16(<8 x half> %a, <8 x half> %b)
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ret <8 x half> %0
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}
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declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
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define arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vminnmq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vminnm.f32 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %0
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}
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declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
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define arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vminnmq_m_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vminnmt.f16 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = tail call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, i32 0, <8 x i1> %1, <8 x half> %inactive)
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ret <8 x half> %2
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}
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
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declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>, <8 x half>) #2
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define arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vminnmq_m_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vminnmt.f32 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = tail call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, i32 0, <4 x i1> %1, <4 x float> %inactive)
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ret <4 x float> %2
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}
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
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declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>, <4 x float>) #2
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define arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vminnmq_x_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vminnmt.f16 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = tail call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, i32 0, <8 x i1> %1, <8 x half> undef)
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ret <8 x half> %2
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}
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define arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
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; CHECK-LABEL: test_vminnmq_x_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vminnmt.f32 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = tail call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, i32 0, <4 x i1> %1, <4 x float> undef)
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ret <4 x float> %2
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}
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