276 lines
15 KiB
Plaintext
276 lines
15 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops -tail-predication=enabled %s -o - | FileCheck %s
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# TODOD: As far as I can tell this test is fine. The tail predicating the second loop means we remove the instruction that would otherwise block the first.
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--- |
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define arm_aapcs_vfpcc void @arm_var_f32_mve(float* %pSrc, i32 %blockSize, float* nocapture %pResult) #0 {
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entry:
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%0 = add i32 %blockSize, 3
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%1 = icmp slt i32 %blockSize, 4
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%smin = select i1 %1, i32 %blockSize, i32 4
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%2 = sub i32 %0, %smin
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%3 = lshr i32 %2, 2
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%4 = add nuw nsw i32 %3, 1
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%5 = icmp slt i32 %blockSize, 4
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%smin3 = select i1 %5, i32 %blockSize, i32 4
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%6 = sub i32 %0, %smin3
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%7 = lshr i32 %6, 2
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%8 = add nuw nsw i32 %7, 1
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%start1 = call i32 @llvm.start.loop.iterations.i32(i32 %8)
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br label %do.body.i
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do.body.i: ; preds = %do.body.i, %entry
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%blkCnt.0.i = phi i32 [ %13, %do.body.i ], [ %blockSize, %entry ]
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%sumVec.0.i = phi <4 x float> [ %12, %do.body.i ], [ zeroinitializer, %entry ]
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%pSrc.addr.0.i = phi float* [ %add.ptr.i, %do.body.i ], [ %pSrc, %entry ]
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%9 = phi i32 [ %start1, %entry ], [ %14, %do.body.i ]
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%pSrc.addr.0.i2 = bitcast float* %pSrc.addr.0.i to <4 x float>*
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%10 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0.i)
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%11 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %pSrc.addr.0.i2, i32 4, <4 x i1> %10, <4 x float> zeroinitializer)
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%12 = tail call fast <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %sumVec.0.i, <4 x float> %11, <4 x i1> %10, <4 x float> %sumVec.0.i)
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%add.ptr.i = getelementptr inbounds float, float* %pSrc.addr.0.i, i32 4
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%13 = add i32 %blkCnt.0.i, -4
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%14 = call i32 @llvm.loop.decrement.reg.i32(i32 %9, i32 1)
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%15 = icmp ne i32 %14, 0
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br i1 %15, label %do.body.i, label %arm_mean_f32_mve.exit
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arm_mean_f32_mve.exit: ; preds = %do.body.i
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%16 = extractelement <4 x float> %12, i32 3
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%add2.i.i = fadd fast float %16, %16
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%conv.i = uitofp i32 %blockSize to float
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%div.i = fdiv fast float %add2.i.i, %conv.i
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%17 = bitcast float %div.i to i32
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%18 = insertelement <4 x i32> undef, i32 %17, i64 0
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%19 = shufflevector <4 x i32> %18, <4 x i32> undef, <4 x i32> zeroinitializer
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%20 = bitcast <4 x i32> %19 to <4 x float>
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%start2 = call i32 @llvm.start.loop.iterations.i32(i32 %4)
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br label %do.body
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do.body: ; preds = %do.body, %arm_mean_f32_mve.exit
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%blkCnt.0 = phi i32 [ %blockSize, %arm_mean_f32_mve.exit ], [ %26, %do.body ]
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%sumVec.0 = phi <4 x float> [ zeroinitializer, %arm_mean_f32_mve.exit ], [ %25, %do.body ]
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%pSrc.addr.0 = phi float* [ %pSrc, %arm_mean_f32_mve.exit ], [ %add.ptr, %do.body ]
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%21 = phi i32 [ %start2, %arm_mean_f32_mve.exit ], [ %27, %do.body ]
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%pSrc.addr.01 = bitcast float* %pSrc.addr.0 to <4 x float>*
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%22 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
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%23 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %pSrc.addr.01, i32 4, <4 x i1> %22, <4 x float> zeroinitializer)
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%24 = tail call fast <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %23, <4 x float> %20, <4 x i1> %22, <4 x float> undef)
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%25 = tail call fast <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %24, <4 x float> %24, <4 x float> %sumVec.0, <4 x i1> %22)
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%add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4
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%26 = add i32 %blkCnt.0, -4
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%27 = call i32 @llvm.loop.decrement.reg.i32(i32 %21, i32 1)
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%28 = icmp ne i32 %27, 0
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br i1 %28, label %do.body, label %do.end
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do.end: ; preds = %do.body
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%29 = extractelement <4 x float> %25, i32 3
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%add2.i = fadd fast float %29, %29
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%sub2 = add i32 %blockSize, -1
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%conv = uitofp i32 %sub2 to float
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%div = fdiv fast float %add2.i, %conv
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store float %div, float* %pResult, align 4
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>) #1
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; Function Attrs: nounwind readnone
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declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
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; Function Attrs: argmemonly nounwind readonly willreturn
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declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #2
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.start.loop.iterations.i32(i32) #3
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #3
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attributes #0 = { "target-features"="+mve.fp" }
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attributes #1 = { nounwind readnone "target-features"="+mve.fp" }
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attributes #2 = { argmemonly nounwind readonly willreturn "target-features"="+mve.fp" }
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attributes #3 = { noduplicate nounwind }
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...
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---
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name: arm_var_f32_mve
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: arm_var_f32_mve
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r4
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
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; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
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; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
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; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
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; CHECK: $r4 = tMOVr $lr, 14 /* CC::al */, $noreg
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; CHECK: bb.1.do.body.i:
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; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r4, $r12
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; CHECK: renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.pSrc.addr.0.i2, align 4)
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; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
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; CHECK: bb.2.arm_mean_f32_mve.exit:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
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; CHECK: $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg
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; CHECK: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg
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; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
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; CHECK: $lr = t2DLS killed $r4
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; CHECK: renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg
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; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg
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; CHECK: renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg
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; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
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; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1
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; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
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; CHECK: bb.3.do.body:
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; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
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; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3
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; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
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; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
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; CHECK: MVE_VPST 2, implicit $vpr
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; CHECK: renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.01, align 4)
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; CHECK: renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2
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; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr
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; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3
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; CHECK: bb.4.do.end:
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; CHECK: liveins: $q0, $r1, $r2
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; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
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; CHECK: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
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; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
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; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
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; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.pResult)
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; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1, $r2, $r4, $lr
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frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r4, -8
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$r3 = tMOVr $r1, 14 /* CC::al */, $noreg
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tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2IT 10, 8, implicit-def $itstate
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renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
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renamable $r12 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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renamable $r3, dead $cpsr = tSUBrr renamable $r1, killed renamable $r3, 14 /* CC::al */, $noreg
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renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
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renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg
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renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
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$r3 = tMOVr $r1, 14 /* CC::al */, $noreg
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$r12 = tMOVr $r0, 14 /* CC::al */, $noreg
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$lr = t2DoLoopStart renamable $lr
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$r4 = tMOVr $lr, 14 /* CC::al */, $noreg
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bb.1.do.body.i:
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successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r12
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renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
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renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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MVE_VPST 4, implicit $vpr
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renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.0.i2, align 4)
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renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0
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t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
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tB %bb.2, 14 /* CC::al */, $noreg
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bb.2.arm_mean_f32_mve.exit:
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successors: %bb.3(0x80000000)
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liveins: $q0, $r0, $r1, $r2, $r4
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$s4 = VMOVSR $r1, 14 /* CC::al */, $noreg
|
||
|
|
$lr = tMOVr $r4, 14 /* CC::al */, $noreg
|
||
|
|
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0
|
||
|
|
$lr = t2DoLoopStart killed $r4
|
||
|
|
renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg
|
||
|
|
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg
|
||
|
|
renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg
|
||
|
|
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
|
||
|
|
renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1
|
||
|
|
$r3 = tMOVr $r1, 14 /* CC::al */, $noreg
|
||
|
|
|
||
|
|
bb.3.do.body:
|
||
|
|
successors: %bb.3(0x7c000000), %bb.4(0x04000000)
|
||
|
|
liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3
|
||
|
|
|
||
|
|
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
|
||
|
|
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
|
||
|
|
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||
|
|
MVE_VPST 2, implicit $vpr
|
||
|
|
renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.01, align 4)
|
||
|
|
renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2
|
||
|
|
renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, renamable $q2, 1, killed renamable $vpr
|
||
|
|
t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
|
||
|
|
tB %bb.4, 14 /* CC::al */, $noreg
|
||
|
|
|
||
|
|
bb.4.do.end:
|
||
|
|
liveins: $q0, $r1, $r2
|
||
|
|
|
||
|
|
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
|
||
|
|
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0
|
||
|
|
$s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
|
||
|
|
renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
|
||
|
|
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
|
||
|
|
VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.pResult)
|
||
|
|
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
|
||
|
|
|
||
|
|
...
|