226 lines
12 KiB
Plaintext
226 lines
12 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
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#
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--- |
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@mask = external global i16
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define dso_local void @test(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i32* noalias nocapture readonly %arg3) local_unnamed_addr #0 {
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bb:
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%tmp = icmp eq i32 %arg2, 0
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%tmp1 = add i32 %arg2, 3
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%tmp2 = lshr i32 %tmp1, 2
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%tmp3 = shl nuw i32 %tmp2, 2
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%tmp4 = add i32 %tmp3, -4
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%tmp5 = lshr i32 %tmp4, 2
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%tmp6 = add nuw nsw i32 %tmp5, 1
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%mask.gep9 = bitcast i16* @mask to i16*
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%mask.load = load i16, i16* %mask.gep9
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%conv.mask = zext i16 %mask.load to i32
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%invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask)
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br i1 %tmp, label %bb27, label %bb3
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bb3: ; preds = %bb
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp6)
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%scevgep1 = getelementptr i32, i32* %arg3, i32 -4
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br label %bb9
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bb9: ; preds = %bb9, %bb3
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%lsr.iv4 = phi i32* [ %scevgep6, %bb9 ], [ %scevgep1, %bb3 ]
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%lsr.iv2 = phi i32* [ %scevgep3, %bb9 ], [ %arg1, %bb3 ]
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%lsr.iv = phi i32* [ %scevgep, %bb9 ], [ %arg, %bb3 ]
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%tmp7 = phi i32 [ %start, %bb3 ], [ %tmp12, %bb9 ]
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%tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ]
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%lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>*
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%lsr.iv24 = bitcast i32* %lsr.iv2 to <4 x i32>*
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%lsr.iv47 = bitcast i32* %lsr.iv4 to <4 x i32>*
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%vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8)
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%and = and <4 x i1> %vctp, %invariant.mask
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%tmp11 = sub i32 %tmp8, 4
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%tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef)
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%tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1, i32 4, <4 x i1> %and, <4 x i32> undef)
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%tmp23 = mul nsw <4 x i32> %tmp22, %tmp17
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%scevgep2 = getelementptr <4 x i32>, <4 x i32>* %lsr.iv47, i32 1
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%load.limits = load <4 x i32>, <4 x i32>* %scevgep2
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%0 = insertelement <4 x i32> undef, i32 %conv.mask, i32 0
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%1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
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%bad.icmp = icmp ule <4 x i32> %load.limits, %1
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call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %tmp23, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %bad.icmp)
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%tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1)
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%tmp13 = icmp ne i32 %tmp12, 0
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%scevgep = getelementptr i32, i32* %lsr.iv, i32 4
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%scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 4
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%scevgep6 = getelementptr i32, i32* %lsr.iv4, i32 4
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br i1 %tmp13, label %bb9, label %bb27
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bb27: ; preds = %bb9, %bb
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ret void
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}
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
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declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
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declare <4 x i1> @llvm.arm.mve.vctp32(i32)
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
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...
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---
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name: test
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 20
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 4, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: test
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; CHECK: bb.0.bb:
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; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
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; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
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; CHECK: tCBZ $r2, %bb.3
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; CHECK: bb.1.bb3:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2, $r3
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; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 /* CC::al */, $noreg
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; CHECK: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
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; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 /* CC::al */, $noreg
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; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 2 from %ir.mask.gep9)
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; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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; CHECK: $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg
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; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
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; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
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; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0
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; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
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; CHECK: $lr = t2DLS killed renamable $lr
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; CHECK: bb.2.bb9:
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; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
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; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
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; CHECK: MVE_VPST 2, implicit $vpr
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; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
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; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
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; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
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; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
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; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8)
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; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
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; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
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; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
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; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
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; CHECK: bb.3.bb27:
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; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
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bb.0.bb:
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successors: %bb.3(0x30000000), %bb.1(0x50000000)
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liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
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frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 16
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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frame-setup CFI_INSTRUCTION offset $r5, -12
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frame-setup CFI_INSTRUCTION offset $r4, -16
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$sp = frame-setup tSUBspi $sp, 1, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_offset 20
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tCBZ $r2, %bb.3
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bb.1.bb3:
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successors: %bb.2(0x80000000)
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liveins: $r0, $r1, $r2, $r3
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$r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg
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renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
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$r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg
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renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg
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renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9)
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renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg
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renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
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$vpr = VMSR_P0 $r5, 14, $noreg
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renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg
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renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg
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VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0)
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renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0
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$r3 = tMOVr $r0, 14, $noreg
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$lr = t2DoLoopStart renamable $lr
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bb.2.bb9:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
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renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0)
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MVE_VPST 2, implicit $vpr
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renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
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renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
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renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
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renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
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renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
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renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8)
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MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
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MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
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renamable $lr = t2LoopDec killed renamable $lr, 1
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$r0 = tMOVr $r3, 14, $noreg
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t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14, $noreg
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bb.3.bb27:
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$sp = tADDspi $sp, 1, 14, $noreg
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tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
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...
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