100 lines
2.4 KiB
LLVM
100 lines
2.4 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Test that the case of (64 - shift) used by a shift/rotate instruction is
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; implemented with an lcr. This should also work for any multiple of 64.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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define i64 @f1(i64 %in, i64 %sh) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lcr %r1, %r3
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; CHECK-NEXT: sllg %r2, %r2, 0(%r1)
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; CHECK-NEXT: br %r14
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%sub = sub i64 64, %sh
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%shl = shl i64 %in, %sub
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ret i64 %shl
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}
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define i64 @f2(i64 %in, i64 %sh) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lcr %r1, %r3
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; CHECK-NEXT: srag %r2, %r2, 0(%r1)
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; CHECK-NEXT: br %r14
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%sub = sub i64 64, %sh
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%shl = ashr i64 %in, %sub
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ret i64 %shl
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}
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define i64 @f3(i64 %in, i64 %sh) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lcr %r1, %r3
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; CHECK-NEXT: srlg %r2, %r2, 0(%r1)
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; CHECK-NEXT: br %r14
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%sub = sub i64 64, %sh
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%shl = lshr i64 %in, %sub
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ret i64 %shl
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}
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define i64 @f4(i64 %in, i64 %sh) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lcr %r1, %r3
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; CHECK-NEXT: rllg %r2, %r2, 0(%r1)
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; CHECK-NEXT: br %r14
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%shr = lshr i64 %in, %sh
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%sub = sub i64 64, %sh
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%shl = shl i64 %in, %sub
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%or = or i64 %shl, %shr
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ret i64 %or
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}
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define i64 @f5(i64 %in, i64 %sh) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lcr %r1, %r3
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; CHECK-NEXT: sllg %r2, %r2, 0(%r1)
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; CHECK-NEXT: br %r14
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%sub = sub i64 128, %sh
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%shl = shl i64 %in, %sub
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ret i64 %shl
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}
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define i64 @f6(i64 %in, i64 %sh) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lcr %r1, %r3
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; CHECK-NEXT: srag %r2, %r2, 0(%r1)
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; CHECK-NEXT: br %r14
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%sub = sub i64 256, %sh
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%shl = ashr i64 %in, %sub
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ret i64 %shl
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}
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define i64 @f7(i64 %in, i64 %sh) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lcr %r1, %r3
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; CHECK-NEXT: srlg %r2, %r2, 0(%r1)
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; CHECK-NEXT: br %r14
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%sub = sub i64 512, %sh
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%shl = lshr i64 %in, %sub
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ret i64 %shl
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}
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define i64 @f8(i64 %in, i64 %sh) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lcr %r1, %r3
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; CHECK-NEXT: srlg %r0, %r2, 0(%r3)
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; CHECK-NEXT: sllg %r2, %r2, 0(%r1)
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; CHECK-NEXT: ogr %r2, %r0
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; CHECK-NEXT: br %r14
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%shr = lshr i64 %in, %sh
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%sub = sub i64 1024, %sh
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%shl = shl i64 %in, %sub
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%or = or i64 %shl, %shr
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ret i64 %or
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}
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