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llvm-for-llvmta/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll

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2022-04-25 10:02:23 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
; RUN: --riscv-no-aliases < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
<vscale x 1 x i8>,
i8,
i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
<vscale x 2 x i8>,
i8,
i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1>,
<vscale x 2 x i8>,
i8,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0,
<vscale x 2 x i8> %1,
i8 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
<vscale x 4 x i8>,
i8,
i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1>,
<vscale x 4 x i8>,
i8,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0,
<vscale x 4 x i8> %1,
i8 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
<vscale x 8 x i8>,
i8,
i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1>,
<vscale x 8 x i8>,
i8,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0,
<vscale x 8 x i8> %1,
i8 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
<vscale x 16 x i8>,
i8,
i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1>,
<vscale x 16 x i8>,
i8,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0,
<vscale x 16 x i8> %1,
i8 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
<vscale x 32 x i8>,
i8,
i64);
define <vscale x 32 x i1> @intrinsic_vmsgtu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 %1,
i64 %2)
ret <vscale x 32 x i1> %a
}
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1>,
<vscale x 32 x i8>,
i8,
<vscale x 32 x i1>,
i64);
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0,
<vscale x 32 x i8> %1,
i8 %2,
<vscale x 32 x i1> %3,
i64 %4)
ret <vscale x 32 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
<vscale x 1 x i16>,
i16,
i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1>,
<vscale x 1 x i16>,
i16,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0,
<vscale x 1 x i16> %1,
i16 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
<vscale x 2 x i16>,
i16,
i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1>,
<vscale x 2 x i16>,
i16,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0,
<vscale x 2 x i16> %1,
i16 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
<vscale x 4 x i16>,
i16,
i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1>,
<vscale x 4 x i16>,
i16,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0,
<vscale x 4 x i16> %1,
i16 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
<vscale x 8 x i16>,
i16,
i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1>,
<vscale x 8 x i16>,
i16,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0,
<vscale x 8 x i16> %1,
i16 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
<vscale x 16 x i16>,
i16,
i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 %1,
i64 %2)
ret <vscale x 16 x i1> %a
}
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1>,
<vscale x 16 x i16>,
i16,
<vscale x 16 x i1>,
i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0,
<vscale x 16 x i16> %1,
i16 %2,
<vscale x 16 x i1> %3,
i64 %4)
ret <vscale x 16 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
<vscale x 1 x i32>,
i32,
i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1>,
<vscale x 1 x i32>,
i32,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0,
<vscale x 1 x i32> %1,
i32 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
<vscale x 2 x i32>,
i32,
i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1>,
<vscale x 2 x i32>,
i32,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0,
<vscale x 2 x i32> %1,
i32 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
<vscale x 4 x i32>,
i32,
i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1>,
<vscale x 4 x i32>,
i32,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0,
<vscale x 4 x i32> %1,
i32 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
<vscale x 8 x i32>,
i32,
i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 %1,
i64 %2)
ret <vscale x 8 x i1> %a
}
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1>,
<vscale x 8 x i32>,
i32,
<vscale x 8 x i1>,
i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0,
<vscale x 8 x i32> %1,
i32 %2,
<vscale x 8 x i1> %3,
i64 %4)
ret <vscale x 8 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
<vscale x 1 x i64>,
i64,
i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
i64 %4)
ret <vscale x 1 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
<vscale x 2 x i64>,
i64,
i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 2 x i1> %a
}
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1>,
<vscale x 2 x i64>,
i64,
<vscale x 2 x i1>,
i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0,
<vscale x 2 x i64> %1,
i64 %2,
<vscale x 2 x i1> %3,
i64 %4)
ret <vscale x 2 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
<vscale x 4 x i64>,
i64,
i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vmsgtu.vx v0, v8, a0
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 %1,
i64 %2)
ret <vscale x 4 x i1> %a
}
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1>,
<vscale x 4 x i64>,
i64,
<vscale x 4 x i1>,
i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0,
<vscale x 4 x i64> %1,
i64 %2,
<vscale x 4 x i1> %3,
i64 %4)
ret <vscale x 4 x i1> %a
}
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 1 x i1> %a
}
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0,
<vscale x 1 x i8> %1,
i8 9,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i1> %a
}
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 2 x i1> %a
}
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0,
<vscale x 2 x i8> %1,
i8 9,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i1> %a
}
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 4 x i1> %a
}
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0,
<vscale x 4 x i8> %1,
i8 9,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i1> %a
}
define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 8 x i1> %a
}
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0,
<vscale x 8 x i8> %1,
i8 9,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i1> %a
}
define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 16 x i1> %a
}
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0,
<vscale x 16 x i8> %1,
i8 9,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i1> %a
}
define <vscale x 32 x i1> @intrinsic_vmsgtu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 32 x i1> %a
}
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0,
<vscale x 32 x i8> %1,
i8 9,
<vscale x 32 x i1> %2,
i64 %3)
ret <vscale x 32 x i1> %a
}
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 1 x i1> %a
}
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0,
<vscale x 1 x i16> %1,
i16 9,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i1> %a
}
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 2 x i1> %a
}
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0,
<vscale x 2 x i16> %1,
i16 9,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i1> %a
}
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 4 x i1> %a
}
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0,
<vscale x 4 x i16> %1,
i16 9,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i1> %a
}
define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 8 x i1> %a
}
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0,
<vscale x 8 x i16> %1,
i16 9,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i1> %a
}
define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 16 x i1> %a
}
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0,
<vscale x 16 x i16> %1,
i16 9,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i1> %a
}
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 9,
i64 %1)
ret <vscale x 1 x i1> %a
}
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0,
<vscale x 1 x i32> %1,
i32 9,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i1> %a
}
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 9,
i64 %1)
ret <vscale x 2 x i1> %a
}
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0,
<vscale x 2 x i32> %1,
i32 9,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i1> %a
}
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 9,
i64 %1)
ret <vscale x 4 x i1> %a
}
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0,
<vscale x 4 x i32> %1,
i32 9,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i1> %a
}
define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 9,
i64 %1)
ret <vscale x 8 x i1> %a
}
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0,
<vscale x 8 x i32> %1,
i32 9,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i1> %a
}
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 9,
i64 %1)
ret <vscale x 1 x i1> %a
}
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0,
<vscale x 1 x i64> %1,
i64 9,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i1> %a
}
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 9,
i64 %1)
ret <vscale x 2 x i1> %a
}
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0,
<vscale x 2 x i64> %1,
i64 9,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i1> %a
}
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vmsgtu.vi v0, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 9,
i64 %1)
ret <vscale x 4 x i1> %a
}
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0,
<vscale x 4 x i64> %1,
i64 9,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i1> %a
}