42 lines
1.2 KiB
LLVM
42 lines
1.2 KiB
LLVM
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; RUN: llc -verify-machineinstrs -enable-misched -misched=shuffle -enable-aa-sched-mi -use-tbaa-in-sched-mi=0 -post-RA-scheduler=0 -mcpu=ppc64 < %s | FileCheck %s
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; REQUIRES: asserts
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; -misched=shuffle is NDEBUG only!
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%"class.llvm::MCOperand" = type { i8, %union.anon.110 }
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%union.anon.110 = type { i64 }
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define void @foo(i32 %v) {
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entry:
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%MCOp = alloca %"class.llvm::MCOperand", align 8
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br label %next
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; CHECK-LABEL: @foo
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next:
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%sunkaddr18 = ptrtoint %"class.llvm::MCOperand"* %MCOp to i64
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%sunkaddr19 = add i64 %sunkaddr18, 8
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%sunkaddr20 = inttoptr i64 %sunkaddr19 to double*
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store double 0.000000e+00, double* %sunkaddr20, align 8, !tbaa !1
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%sunkaddr21 = ptrtoint %"class.llvm::MCOperand"* %MCOp to i64
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%sunkaddr22 = add i64 %sunkaddr21, 8
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%sunkaddr23 = inttoptr i64 %sunkaddr22 to i32*
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store i32 %v, i32* %sunkaddr23, align 8, !tbaa !2
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ret void
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; Make sure that the 64-bit store comes first, regardless of what TBAA says
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; about the two not aliasing!
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; CHECK: li [[REG:[0-9]+]], 0
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; CHECK: std [[REG]], -[[OFF:[0-9]+]](1)
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; CHECK: stw 3, -[[OFF]](1)
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; CHECK: blr
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}
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!0 = !{ !"root" }
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!1 = !{ !"set1", !0 }
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!2 = !{ !"set2", !0 }
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