180 lines
7.5 KiB
LLVM
180 lines
7.5 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Make sure we generate a hardware loop and pipeline the inner loop using
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; 4 packets, which is equivalent to the hand-coded version.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: {
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; CHECK: }
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; CHECK: {
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; CHECK: }
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; CHECK: {
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; CHECK: }
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; CHECK: {
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; CHECK: }
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; CHECK: {
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; CHECK-NOT: }
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; CHECK: }{{[ \t]*}}:endloop0
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define void @f0(i8* noalias %a0, i32 %a1, i32 %a2, i32 %a3, i8* noalias nocapture %a4, i32 %a5, i32 %a6) #0 {
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b0:
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%v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 8388736)
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%v1 = zext i32 %a3 to i64
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%v2 = shl nuw i64 %v1, 32
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%v3 = zext i32 %a1 to i64
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%v4 = shl nuw nsw i64 %v3, 16
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%v5 = or i64 %v4, %v2
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%v6 = or i64 %v5, 281474976710658
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tail call void asm sideeffect " l2fetch($0, $1)\0A", "r,r"(i8* %a0, i64 %v6) #2, !srcloc !0
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%v7 = tail call i32 @llvm.hexagon.S2.ct0(i32 %a6)
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%v8 = add i32 %v7, 1
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%v9 = lshr i32 %a1, %v8
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%v10 = mul i32 %a6, 2
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%v11 = mul i32 %v10, %v9
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%v12 = sub i32 %a1, %v11
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%v13 = lshr i32 %v12, 1
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%v14 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v13)
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%v15 = icmp eq i32 %a2, 0
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br i1 %v15, label %b11, label %b1
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b1: ; preds = %b0
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%v16 = mul i32 %a3, 2
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%v17 = icmp eq i32 %v9, 0
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%v18 = icmp eq i32 %v11, %a1
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%v19 = icmp ugt i32 %v12, %a6
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%v20 = mul i32 %v9, 64
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%v21 = getelementptr i8, i8* %a4, i32 %v20
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%v22 = mul i32 %v9, 128
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%v23 = add i32 %v22, %a3
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%v24 = getelementptr i8, i8* %a0, i32 %v23
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%v25 = getelementptr i8, i8* %a0, i32 %v22
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br label %b2
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b2: ; preds = %b10, %b1
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%v26 = phi i8* [ %v25, %b1 ], [ %v90, %b10 ]
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%v27 = phi i8* [ %v24, %b1 ], [ %v89, %b10 ]
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%v28 = phi i8* [ %v21, %b1 ], [ %v88, %b10 ]
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%v29 = phi <16 x i32> [ undef, %b1 ], [ %v85, %b10 ]
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%v30 = phi <16 x i32> [ undef, %b1 ], [ %v84, %b10 ]
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%v31 = phi i8* [ %a0, %b1 ], [ %v86, %b10 ]
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%v32 = phi i8* [ %a4, %b1 ], [ %v87, %b10 ]
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%v33 = phi i32 [ 0, %b1 ], [ %v37, %b10 ]
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%v34 = bitcast i8* %v26 to <16 x i32>*
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%v35 = bitcast i8* %v27 to <16 x i32>*
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%v36 = bitcast i8* %v28 to <16 x i32>*
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%v37 = add nsw i32 %v33, 2
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%v38 = icmp ult i32 %v37, %a2
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br i1 %v38, label %b3, label %b4
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b3: ; preds = %b2
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%v39 = getelementptr inbounds i8, i8* %v31, i32 %v16
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tail call void asm sideeffect " l2fetch($0, $1)\0A", "r,r"(i8* %v39, i64 %v6) #2, !srcloc !1
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br label %b4
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b4: ; preds = %b3, %b2
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%v40 = bitcast i8* %v32 to <16 x i32>*
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%v41 = bitcast i8* %v31 to <16 x i32>*
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%v42 = getelementptr inbounds i8, i8* %v31, i32 %a3
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%v43 = bitcast i8* %v42 to <16 x i32>*
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br i1 %v17, label %b6, label %b5
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b5: ; preds = %b5, %b4
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%v44 = phi <16 x i32>* [ %v54, %b5 ], [ %v43, %b4 ]
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%v45 = phi <16 x i32>* [ %v52, %b5 ], [ %v41, %b4 ]
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%v46 = phi <16 x i32>* [ %v61, %b5 ], [ %v40, %b4 ]
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%v47 = phi i32 [ %v62, %b5 ], [ 0, %b4 ]
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%v48 = getelementptr inbounds <16 x i32>, <16 x i32>* %v45, i32 1
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%v49 = load <16 x i32>, <16 x i32>* %v45, align 64, !tbaa !2
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%v50 = getelementptr inbounds <16 x i32>, <16 x i32>* %v44, i32 1
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%v51 = load <16 x i32>, <16 x i32>* %v44, align 64, !tbaa !2
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%v52 = getelementptr inbounds <16 x i32>, <16 x i32>* %v45, i32 2
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%v53 = load <16 x i32>, <16 x i32>* %v48, align 64, !tbaa !2
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%v54 = getelementptr inbounds <16 x i32>, <16 x i32>* %v44, i32 2
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%v55 = load <16 x i32>, <16 x i32>* %v50, align 64, !tbaa !2
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%v56 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v49, i32 1077952576)
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%v57 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v53, i32 1077952576)
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%v58 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v56, <16 x i32> %v51, i32 1077952576)
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%v59 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v57, <16 x i32> %v55, i32 1077952576)
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%v60 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %v59, <16 x i32> %v58)
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%v61 = getelementptr inbounds <16 x i32>, <16 x i32>* %v46, i32 1
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store <16 x i32> %v60, <16 x i32>* %v46, align 64, !tbaa !2
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%v62 = add nsw i32 %v47, 1
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%v63 = icmp eq i32 %v62, %v9
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br i1 %v63, label %b6, label %b5
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b6: ; preds = %b5, %b4
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%v64 = phi <16 x i32> [ %v29, %b4 ], [ %v55, %b5 ]
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%v65 = phi <16 x i32> [ %v30, %b4 ], [ %v53, %b5 ]
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%v66 = phi <16 x i32>* [ %v43, %b4 ], [ %v35, %b5 ]
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%v67 = phi <16 x i32>* [ %v41, %b4 ], [ %v34, %b5 ]
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%v68 = phi <16 x i32>* [ %v40, %b4 ], [ %v36, %b5 ]
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br i1 %v18, label %b10, label %b7
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b7: ; preds = %b6
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%v69 = load <16 x i32>, <16 x i32>* %v67, align 64, !tbaa !2
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%v70 = load <16 x i32>, <16 x i32>* %v66, align 64, !tbaa !2
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br i1 %v19, label %b8, label %b9
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b8: ; preds = %b7
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%v71 = getelementptr inbounds <16 x i32>, <16 x i32>* %v66, i32 1
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%v72 = getelementptr inbounds <16 x i32>, <16 x i32>* %v67, i32 1
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%v73 = load <16 x i32>, <16 x i32>* %v72, align 64, !tbaa !2
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%v74 = load <16 x i32>, <16 x i32>* %v71, align 64, !tbaa !2
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br label %b9
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b9: ; preds = %b8, %b7
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%v75 = phi <16 x i32> [ %v73, %b8 ], [ %v65, %b7 ]
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%v76 = phi <16 x i32> [ %v74, %b8 ], [ %v64, %b7 ]
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%v77 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v69, i32 1077952576)
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%v78 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v75, i32 1077952576)
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%v79 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v77, <16 x i32> %v70, i32 1077952576)
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%v80 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v78, <16 x i32> %v76, i32 1077952576)
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%v81 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %v80, <16 x i32> %v79)
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%v82 = load <16 x i32>, <16 x i32>* %v68, align 64, !tbaa !2
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%v83 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v14, <16 x i32> %v81, <16 x i32> %v82)
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store <16 x i32> %v83, <16 x i32>* %v68, align 64, !tbaa !2
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br label %b10
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b10: ; preds = %b9, %b6
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%v84 = phi <16 x i32> [ %v75, %b9 ], [ %v65, %b6 ]
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%v85 = phi <16 x i32> [ %v76, %b9 ], [ %v64, %b6 ]
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%v86 = getelementptr inbounds i8, i8* %v31, i32 %v16
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%v87 = getelementptr inbounds i8, i8* %v32, i32 %a5
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%v88 = getelementptr i8, i8* %v28, i32 %a5
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%v89 = getelementptr i8, i8* %v27, i32 %v16
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%v90 = getelementptr i8, i8* %v26, i32 %v16
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br i1 %v38, label %b2, label %b11
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b11: ; preds = %b10, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.ct0(i32) #1
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; Function Attrs: nounwind readnone
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declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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!0 = !{i32 -2146401371}
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!1 = !{i32 -2146401153}
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!2 = !{!3, !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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