47 lines
1.5 KiB
LLVM
47 lines
1.5 KiB
LLVM
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; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
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; Make sure we generate stack alignment.
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; CHECK: [[REG1:r[0-9]*]] = and(r29,#-64)
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; CHECK: = add([[REG1]],#128)
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; CHECK: = add([[REG1]],#64)
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; Make sure we do not generate another -64 off SP.
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; CHECK: vmem(
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; CHECK-NOT: r{{[0-9]*}} = add(r29,#-64)
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target triple = "hexagon"
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@g0 = common global <16 x i32> zeroinitializer, align 64
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; Function Attrs: nounwind
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define i32 @f0() #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = alloca <16 x i32>, align 64
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%v2 = alloca <16 x i32>, align 64
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store i32 0, i32* %v0
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%v3 = call i32 @f1(i8 zeroext 0)
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%v4 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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store <16 x i32> %v4, <16 x i32>* %v1, align 64
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%v5 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 12)
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store <16 x i32> %v5, <16 x i32>* %v2, align 64
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%v6 = load <16 x i32>, <16 x i32>* %v1, align 64
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%v7 = load <16 x i32>, <16 x i32>* %v2, align 64
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%v8 = call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v6, <16 x i32> %v7)
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store <16 x i32> %v8, <16 x i32>* @g0, align 64
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call void bitcast (void (...)* @f2 to void ()*)()
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ret i32 0
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}
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declare i32 @f1(i8 zeroext) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #1
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declare void @f2(...) #0
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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