64 lines
2.4 KiB
LLVM
64 lines
2.4 KiB
LLVM
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; RUN: llc -march=hexagon -O2 -disable-block-placement < %s | FileCheck %s
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; Disable block placement because it intereferes with the generated code.
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; CHECK: if (p{{[0-9]*}}) jump:nt .LBB0_2
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; CHECK-NEXT: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)
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; CHECK-NEXT: }
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target triple = "hexagon"
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@g0 = global <16 x i32> zeroinitializer, align 64
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; Function Attrs: nounwind
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define void @f0(i16* nocapture readonly %a0, i32 %a1, i32 %a2, i16* nocapture %a3) #0 {
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b0:
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%v0 = mul i32 %a2, -2
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%v1 = add i32 %v0, 64
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%v2 = bitcast i16* %a3 to <16 x i32>*
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%v3 = load <16 x i32>, <16 x i32>* @g0, align 64
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%v4 = sdiv i32 %a1, 32
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%v5 = icmp sgt i32 %a1, 31
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br i1 %v5, label %b1, label %b4
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b1: ; preds = %b0
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%v6 = bitcast i16* %a0 to <16 x i32>*
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%v7 = icmp sgt i32 %a1, 63
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%v8 = mul i32 %v4, 32
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%v9 = select i1 %v7, i32 %v8, i32 32
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%v10 = getelementptr i16, i16* %a3, i32 %v9
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br label %b2
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b2: ; preds = %b2, %b1
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%v11 = phi i32 [ 0, %b1 ], [ %v19, %b2 ]
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%v12 = phi <16 x i32> [ %v3, %b1 ], [ %v16, %b2 ]
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%v13 = phi <16 x i32>* [ %v2, %b1 ], [ %v18, %b2 ]
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%v14 = phi <16 x i32>* [ %v6, %b1 ], [ %v15, %b2 ]
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%v15 = getelementptr inbounds <16 x i32>, <16 x i32>* %v14, i32 1
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%v16 = load <16 x i32>, <16 x i32>* %v14, align 64
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%v17 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v16, <16 x i32> %v12, i32 %v1)
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%v18 = getelementptr inbounds <16 x i32>, <16 x i32>* %v13, i32 1
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store <16 x i32> %v17, <16 x i32>* %v13, align 64
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%v19 = add nsw i32 %v11, 1
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%v20 = icmp slt i32 %v19, %v4
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br i1 %v20, label %b2, label %b3
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b3: ; preds = %b2
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%v21 = bitcast i16* %v10 to <16 x i32>*
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%v22 = load <16 x i32>, <16 x i32>* @g0, align 64
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br label %b4
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b4: ; preds = %b3, %b0
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%v23 = phi <16 x i32> [ %v22, %b3 ], [ %v3, %b0 ]
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%v24 = phi <16 x i32> [ %v16, %b3 ], [ %v3, %b0 ]
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%v25 = phi <16 x i32>* [ %v21, %b3 ], [ %v2, %b0 ]
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%v26 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v23, <16 x i32> %v24, i32 %v1)
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store <16 x i32> %v26, <16 x i32>* %v25, align 64
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvxv62,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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