149 lines
4.9 KiB
LLVM
149 lines
4.9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
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declare half @llvm.vector.reduce.fmul.f16.v4f16(half, <4 x half>)
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declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)
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declare double @llvm.vector.reduce.fmul.f64.v2f64(double, <2 x double>)
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declare fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128, <2 x fp128>)
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define half @test_v4f16(<4 x half> %a) nounwind {
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; CHECK-LABEL: test_v4f16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: mov r4, #255
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; CHECK-NEXT: mov r7, r0
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; CHECK-NEXT: orr r4, r4, #65280
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; CHECK-NEXT: mov r5, r2
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; CHECK-NEXT: and r0, r3, r4
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; CHECK-NEXT: mov r6, r1
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r8, r0
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; CHECK-NEXT: and r0, r5, r4
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r5, r0
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; CHECK-NEXT: and r0, r7, r4
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r7, r0
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; CHECK-NEXT: and r0, r6, r4
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; CHECK-NEXT: bl __aeabi_h2f
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; CHECK-NEXT: mov r1, r0
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; CHECK-NEXT: mov r0, r7
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; CHECK-NEXT: bl __aeabi_fmul
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; CHECK-NEXT: mov r1, r5
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; CHECK-NEXT: bl __aeabi_fmul
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; CHECK-NEXT: mov r1, r8
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; CHECK-NEXT: bl __aeabi_fmul
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; CHECK-NEXT: bl __aeabi_f2h
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; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast half @llvm.vector.reduce.fmul.f16.v4f16(half 1.0, <4 x half> %a)
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ret half %b
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}
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define float @test_v4f32(<4 x float> %a) nounwind {
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; CHECK-LABEL: test_v4f32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r11, lr}
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; CHECK-NEXT: push {r4, r5, r11, lr}
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; CHECK-NEXT: mov r4, r3
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; CHECK-NEXT: mov r5, r2
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; CHECK-NEXT: bl __aeabi_fmul
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; CHECK-NEXT: mov r1, r5
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; CHECK-NEXT: bl __aeabi_fmul
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; CHECK-NEXT: mov r1, r4
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; CHECK-NEXT: bl __aeabi_fmul
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; CHECK-NEXT: pop {r4, r5, r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)
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ret float %b
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}
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define float @test_v4f32_strict(<4 x float> %a) nounwind {
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; CHECK-LABEL: test_v4f32_strict:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r11, lr}
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; CHECK-NEXT: push {r4, r5, r11, lr}
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; CHECK-NEXT: mov r4, r3
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; CHECK-NEXT: mov r5, r2
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; CHECK-NEXT: bl __aeabi_fmul
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; CHECK-NEXT: mov r1, r5
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; CHECK-NEXT: bl __aeabi_fmul
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; CHECK-NEXT: mov r1, r4
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; CHECK-NEXT: bl __aeabi_fmul
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; CHECK-NEXT: pop {r4, r5, r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)
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ret float %b
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}
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define double @test_v2f64(<2 x double> %a) nounwind {
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; CHECK-LABEL: test_v2f64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: bl __aeabi_dmul
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; CHECK-NEXT: pop {r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a)
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ret double %b
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}
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define double @test_v2f64_strict(<2 x double> %a) nounwind {
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; CHECK-LABEL: test_v2f64_strict:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: bl __aeabi_dmul
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; CHECK-NEXT: pop {r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %a)
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ret double %b
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}
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define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: ldr r12, [sp, #36]
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; CHECK-NEXT: str r12, [sp, #12]
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; CHECK-NEXT: ldr r12, [sp, #32]
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; CHECK-NEXT: str r12, [sp, #8]
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; CHECK-NEXT: ldr r12, [sp, #28]
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; CHECK-NEXT: str r12, [sp, #4]
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; CHECK-NEXT: ldr r12, [sp, #24]
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; CHECK-NEXT: str r12, [sp]
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; CHECK-NEXT: bl __multf3
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: pop {r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fast fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128 0xL00000000000000003fff00000000000000, <2 x fp128> %a)
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ret fp128 %b
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}
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define fp128 @test_v2f128_strict(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128_strict:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: ldr r12, [sp, #36]
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; CHECK-NEXT: str r12, [sp, #12]
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; CHECK-NEXT: ldr r12, [sp, #32]
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; CHECK-NEXT: str r12, [sp, #8]
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; CHECK-NEXT: ldr r12, [sp, #28]
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; CHECK-NEXT: str r12, [sp, #4]
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; CHECK-NEXT: ldr r12, [sp, #24]
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; CHECK-NEXT: str r12, [sp]
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; CHECK-NEXT: bl __multf3
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: pop {r11, lr}
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; CHECK-NEXT: mov pc, lr
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%b = call fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128 0xL00000000000000003fff00000000000000, <2 x fp128> %a)
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ret fp128 %b
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}
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