57 lines
2.2 KiB
LLVM
57 lines
2.2 KiB
LLVM
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; The failure is caused by ARM LDRcp/PICADD pairs. In PIC mode, the constant pool
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; need a label to do address computation. This label is emitted when backend emits
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; PICADD. When the target becomes dead, PICADD will be deleted. without this patch
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; LDRcp is dead but not being deleted. This will cause a dead contant pool entry
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; using a non existing label. This will cause an error in MC object emitting pass.
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; RUN: llc -relocation-model=pic -mcpu=cortex-a53 %s -filetype=obj -o - | llvm-nm - | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv8-unknown-linux-android"
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@_ZN15UsecaseSelector25AllowedImplDefinedFormatsE = external dso_local unnamed_addr constant <{ i32, i32, i32, i32, [12 x i32] }>, align 4
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; Function Attrs: noinline nounwind optnone sspstrong uwtable
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define dso_local fastcc void @_ZN15UsecaseSelector26IsAllowedImplDefinedFormatE15ChiBufferFormatj() unnamed_addr #1 align 2 {
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br label %1
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; <label>:1: ; preds = %13, %0
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%2 = icmp ult i32 undef, 4
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br i1 %2, label %3, label %14
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; <label>:3: ; preds = %1
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br i1 undef, label %4, label %13
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; <label>:4: ; preds = %3
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%5 = getelementptr inbounds [16 x i32], [16 x i32]* bitcast (<{ i32, i32, i32, i32, [12 x i32] }>* @_ZN15UsecaseSelector25AllowedImplDefinedFormatsE to [16 x i32]*), i32 0, i32 undef
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%6 = load i32, i32* %5, align 4
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%7 = icmp eq i32 10, %6
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br i1 %7, label %9, label %8
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; <label>:8: ; preds = %4
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br i1 undef, label %9, label %12
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; <label>:9: ; preds = %8, %4
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br i1 undef, label %10, label %13
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; <label>:10: ; preds = %9
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br i1 undef, label %11, label %13
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; <label>:11: ; preds = %10
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br label %14
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; <label>:12: ; preds = %8
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br label %14
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; <label>:13: ; preds = %10, %9, %3
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br label %1
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; <label>:14: ; preds = %12, %11, %1
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ret void
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}
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attributes #1 = { noinline optnone }
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; CHECK: _ZN15UsecaseSelector26IsAllowedImplDefinedFormatE15ChiBufferFormatj
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