293 lines
12 KiB
LLVM
293 lines
12 KiB
LLVM
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; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM --check-prefix=ARM-MACHO
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; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM --check-prefix=ARM-ELF
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; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
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; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG --check-prefix=ARM-LONG-MACHO
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; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG --check-prefix=ARM-LONG-ELF
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; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG
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; Note that some of these tests assume that relocations are either
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; movw/movt or constant pool loads. Different platforms will select
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; different approaches.
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@message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1
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@temp = common global [60 x i8] zeroinitializer, align 1
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define void @t1() nounwind ssp {
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; ARM-LABEL: t1:
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; ARM: {{(movw r0, :lower16:_?message1)|(ldr r0, .LCPI)}}
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; ARM: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
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; ARM-DAG: add r0, r0, #5
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; ARM-DAG: movw r1, #64
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; ARM-DAG: movw r2, #10
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; ARM-DAG: and r1, r1, #255
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; ARM: bl {{_?}}memset
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; ARM-LONG-LABEL: t1:
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; ARM-LONG-MACHO: {{(movw r3, :lower16:L_memset\$non_lazy_ptr)|(ldr r3, .LCPI)}}
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; ARM-LONG-MACHO: {{(movt r3, :upper16:L_memset\$non_lazy_ptr)?}}
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; ARM-LONG-MACHO: ldr r3, [r3]
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; ARM-LONG-ELF: movw r3, :lower16:memset
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; ARM-LONG-ELF: movt r3, :upper16:memset
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; ARM-LONG: blx r3
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; THUMB-LABEL: t1:
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; THUMB: {{(movw r0, :lower16:_?message1)|(ldr.n r0, .LCPI)}}
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; THUMB: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
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; THUMB: adds r0, #5
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; THUMB: movs r1, #64
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; THUMB: movs r2, #10
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; THUMB: and r1, r1, #255
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; THUMB: bl {{_?}}memset
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; THUMB-LONG-LABEL: t1:
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; THUMB-LONG: movw r3, :lower16:L_memset$non_lazy_ptr
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; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
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; THUMB-LONG: ldr r3, [r3]
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; THUMB-LONG: blx r3
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call void @llvm.memset.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @message1, i32 0, i32 5), i8 64, i32 10, i1 false)
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ret void
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}
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declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
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define void @t2() nounwind ssp {
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; ARM-LABEL: t2:
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; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
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; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
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; ARM-MACHO: ldr [[REG1:r[0-9]+]], [r0]
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; ARM-MACHO: add r0, [[REG1]], #4
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; ARM-MACHO-NEXT: add r1, [[REG1]], #16
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; ARM-ELF: movw [[REG1:r[0-9]+]], :lower16:temp
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; ARM-ELF: movt [[REG1]], :upper16:temp
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; ARM-ELF: add r0, [[REG1]], #4
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; ARM-ELF-NEXT: add r1, [[REG1]], #16
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; ARM: movw r2, #17
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; ARM: bl {{_?}}memcpy
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; ARM-LONG-LABEL: t2:
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; ARM-LONG-MACHO: {{(movw r3, :lower16:L_memcpy\$non_lazy_ptr)|(ldr r3, .LCPI)}}
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; ARM-LONG-MACHO: {{(movt r3, :upper16:L_memcpy\$non_lazy_ptr)?}}
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; ARM-LONG-MACHO: ldr r3, [r3]
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; ARM-LONG-ELF: movw r3, :lower16:memcpy
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; ARM-LONG-ELF: movt r3, :upper16:memcpy
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; ARM-LONG: blx r3
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; THUMB-LABEL: t2:
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; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
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; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
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; THUMB: ldr [[REG1:r[0-9]+]], [r0]
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; THUMB: adds r0, [[REG1]], #4
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; THUMB: adds r1, #16
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; THUMB: movs r2, #17
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; THUMB: bl {{_?}}memcpy
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; THUMB-LONG-LABEL: t2:
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; THUMB-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr
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; THUMB-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr
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; THUMB-LONG: ldr r3, [r3]
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; THUMB-LONG: blx r3
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 17, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
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define void @t3() nounwind ssp {
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; ARM-LABEL: t3:
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; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
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; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
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; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
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; ARM-MACHO: add r0, [[REG0]], #4
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; ARM-MACHO-NEXT: add r1, [[REG0]], #16
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; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
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; ARM-ELF: movt [[REG0]], :upper16:temp
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; ARM-ELF: add r0, [[REG0]], #4
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; ARM-ELF-NEXT: add r1, r1, #16
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; ARM: movw r2, #10
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; ARM: bl {{_?}}memmove
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; ARM-LONG-LABEL: t3:
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; ARM-LONG-MACHO: {{(movw r3, :lower16:L_memmove\$non_lazy_ptr)|(ldr r3, .LCPI)}}
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; ARM-LONG-MACHO: {{(movt r3, :upper16:L_memmove\$non_lazy_ptr)?}}
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; ARM-LONG-MACHO: ldr r3, [r3]
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; ARM-LONG-ELF: movw r3, :lower16:memmove
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; ARM-LONG-ELF: movt r3, :upper16:memmove
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; ARM-LONG: blx r3
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; THUMB-LABEL: t3:
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; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
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; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
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; THUMB: ldr [[REG1:r[0-9]+]], [r0]
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; THUMB: adds r0, [[REG1]], #4
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; THUMB: adds r1, #16
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; THUMB: movs r2, #10
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; THUMB: bl {{_?}}memmove
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; THUMB-LONG-LABEL: t3:
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; THUMB-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr
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; THUMB-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr
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; THUMB-LONG: ldr r3, [r3]
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; THUMB-LONG: blx r3
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call void @llvm.memmove.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
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ret void
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}
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define void @t4() nounwind ssp {
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; ARM-LABEL: t4:
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; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
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; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
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; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
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; ARM-MACHO-NEXT: ldr [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
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; ARM-MACHO-NEXT: str [[REG1]], {{\[}}[[REG0]], #4]
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; ARM-MACHO-NEXT: ldr [[REG2:r[0-9]+]], {{\[}}[[REG0]], #20]
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; ARM-MACHO-NEXT: str [[REG2]], {{\[}}[[REG0]], #8]
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; ARM-MACHO-NEXT: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #24]
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; ARM-MACHO-NEXT: strh [[REG3]], {{\[}}[[REG0]], #12]
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; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
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; ARM-ELF: movt [[REG0]], :upper16:temp
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; ARM: bx lr
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; THUMB-LABEL: t4:
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; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
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; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
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; THUMB: ldr [[REG1:r[0-9]+]], [r0]
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; THUMB: ldr [[REG2:r[0-9]+]], {{\[}}[[REG1]], #16]
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; THUMB: str [[REG2]], {{\[}}[[REG1]], #4]
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; THUMB: ldr [[REG3:r[0-9]+]], {{\[}}[[REG1]], #20]
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; THUMB: str [[REG3]], {{\[}}[[REG1]], #8]
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; THUMB: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG1]], #24]
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; THUMB: strh [[REG4]], {{\[}}[[REG1]], #12]
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; THUMB: bx lr
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
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ret void
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}
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declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
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define void @t5() nounwind ssp {
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; ARM-LABEL: t5:
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; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
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; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
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; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
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; ARM-MACHO: ldrh [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
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; ARM-MACHO-NEXT: strh [[REG1]], {{\[}}[[REG0]], #4]
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; ARM-MACHO-NEXT: ldrh [[REG2:r[0-9]+]], {{\[}}[[REG0]], #18]
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; ARM-MACHO-NEXT: strh [[REG2]], {{\[}}[[REG0]], #6]
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; ARM-MACHO-NEXT: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #20]
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; ARM-MACHO-NEXT: strh [[REG3]], {{\[}}[[REG0]], #8]
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; ARM-MACHO-NEXT: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG0]], #22]
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; ARM-MACHO-NEXT: strh [[REG4]], {{\[}}[[REG0]], #10]
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; ARM-MACHO-NEXT: ldrh [[REG5:r[0-9]+]], {{\[}}[[REG0]], #24]
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; ARM-MACHO-NEXT: strh [[REG5]], {{\[}}[[REG0]], #12]
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; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
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; ARM-ELF: movt [[REG0]], :upper16:temp
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; ARM: bx lr
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; THUMB-LABEL: t5:
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; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
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; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
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; THUMB: ldr [[REG1:r[0-9]+]], [r0]
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; THUMB: ldrh [[REG2:r[0-9]+]], {{\[}}[[REG1]], #16]
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; THUMB: strh [[REG2]], {{\[}}[[REG1]], #4]
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; THUMB: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG1]], #18]
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; THUMB: strh [[REG3]], {{\[}}[[REG1]], #6]
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; THUMB: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG1]], #20]
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; THUMB: strh [[REG4]], {{\[}}[[REG1]], #8]
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; THUMB: ldrh [[REG5:r[0-9]+]], {{\[}}[[REG1]], #22]
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; THUMB: strh [[REG5]], {{\[}}[[REG1]], #10]
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; THUMB: ldrh [[REG6:r[0-9]+]], {{\[}}[[REG1]], #24]
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; THUMB: strh [[REG6]], {{\[}}[[REG1]], #12]
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; THUMB: bx lr
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
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ret void
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}
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define void @t6() nounwind ssp {
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; ARM-LABEL: t6:
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; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
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; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
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; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
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; ARM-MACHO: ldrb [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
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; ARM-MACHO-NEXT: strb [[REG1]], {{\[}}[[REG0]], #4]
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; ARM-MACHO-NEXT: ldrb [[REG2:r[0-9]+]], {{\[}}[[REG0]], #17]
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; ARM-MACHO-NEXT: strb [[REG2]], {{\[}}[[REG0]], #5]
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; ARM-MACHO-NEXT: ldrb [[REG3:r[0-9]+]], {{\[}}[[REG0]], #18]
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; ARM-MACHO-NEXT: strb [[REG3]], {{\[}}[[REG0]], #6]
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; ARM-MACHO-NEXT: ldrb [[REG4:r[0-9]+]], {{\[}}[[REG0]], #19]
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; ARM-MACHO-NEXT: strb [[REG4]], {{\[}}[[REG0]], #7]
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; ARM-MACHO-NEXT: ldrb [[REG5:r[0-9]+]], {{\[}}[[REG0]], #20]
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; ARM-MACHO-NEXT: strb [[REG5]], {{\[}}[[REG0]], #8]
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; ARM-MACHO-NEXT: ldrb [[REG6:r[0-9]+]], {{\[}}[[REG0]], #21]
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; ARM-MACHO-NEXT: strb [[REG6]], {{\[}}[[REG0]], #9]
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; ARM-MACHO-NEXT: ldrb [[REG7:r[0-9]+]], {{\[}}[[REG0]], #22]
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; ARM-MACHO-NEXT: strb [[REG7]], {{\[}}[[REG0]], #10]
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; ARM-MACHO-NEXT: ldrb [[REG8:r[0-9]+]], {{\[}}[[REG0]], #23]
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; ARM-MACHO-NEXT: strb [[REG8]], {{\[}}[[REG0]], #11]
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; ARM-MACHO-NEXT: ldrb [[REG9:r[0-9]+]], {{\[}}[[REG0]], #24]
|
||
|
|
; ARM-MACHO-NEXT: strb [[REG9]], {{\[}}[[REG0]], #12]
|
||
|
|
; ARM-MACHO-NEXT: ldrb [[REG10:r[0-9]+]], {{\[}}[[REG0]], #25]
|
||
|
|
; ARM-MACHO-NEXT: strb [[REG10]], {{\[}}[[REG0]], #13]
|
||
|
|
|
||
|
|
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
|
||
|
|
; ARM-ELF: movt [[REG0]], :upper16:temp
|
||
|
|
|
||
|
|
; ARM: bx lr
|
||
|
|
; THUMB-LABEL: t6:
|
||
|
|
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
|
||
|
|
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||
|
|
; THUMB: ldr [[REG0:r[0-9]+]], [r0]
|
||
|
|
; THUMB: ldrb [[REG2:r[0-9]+]], {{\[}}[[REG0]], #16]
|
||
|
|
; THUMB: strb [[REG2]], {{\[}}[[REG0]], #4]
|
||
|
|
; THUMB: ldrb [[REG3:r[0-9]+]], {{\[}}[[REG0]], #17]
|
||
|
|
; THUMB: strb [[REG3]], {{\[}}[[REG0]], #5]
|
||
|
|
; THUMB: ldrb [[REG4:r[0-9]+]], {{\[}}[[REG0]], #18]
|
||
|
|
; THUMB: strb [[REG4]], {{\[}}[[REG0]], #6]
|
||
|
|
; THUMB: ldrb [[REG5:r[0-9]+]], {{\[}}[[REG0]], #19]
|
||
|
|
; THUMB: strb [[REG5]], {{\[}}[[REG0]], #7]
|
||
|
|
; THUMB: ldrb [[REG6:r[0-9]+]], {{\[}}[[REG0]], #20]
|
||
|
|
; THUMB: strb [[REG6]], {{\[}}[[REG0]], #8]
|
||
|
|
; THUMB: ldrb [[REG7:r[0-9]+]], {{\[}}[[REG0]], #21]
|
||
|
|
; THUMB: strb [[REG7]], {{\[}}[[REG0]], #9]
|
||
|
|
; THUMB: ldrb [[REG8:r[0-9]+]], {{\[}}[[REG0]], #22]
|
||
|
|
; THUMB: strb [[REG8]], {{\[}}[[REG0]], #10]
|
||
|
|
; THUMB: ldrb [[REG9:r[0-9]+]], {{\[}}[[REG0]], #23]
|
||
|
|
; THUMB: strb [[REG9]], {{\[}}[[REG0]], #11]
|
||
|
|
; THUMB: ldrb [[REG10:r[0-9]+]], {{\[}}[[REG0]], #24]
|
||
|
|
; THUMB: strb [[REG10]], {{\[}}[[REG0]], #12]
|
||
|
|
; THUMB: ldrb [[REG11:r[0-9]+]], {{\[}}[[REG0]], #25]
|
||
|
|
; THUMB: strb [[REG11]], {{\[}}[[REG0]], #13]
|
||
|
|
; THUMB: bx lr
|
||
|
|
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
; rdar://13202135
|
||
|
|
define void @t7() nounwind ssp {
|
||
|
|
; Just make sure this doesn't assert when we have an odd length and an alignment of 2.
|
||
|
|
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 3, i1 false)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define i32 @t8(i32 %x) nounwind {
|
||
|
|
entry:
|
||
|
|
; ARM-LABEL: t8:
|
||
|
|
; ARM-NOT: FastISel missed call: %expval = call i32 @llvm.expect.i32(i32 %x, i32 1)
|
||
|
|
; THUMB-LABEL: t8:
|
||
|
|
; THUMB-NOT: FastISel missed call: %expval = call i32 @llvm.expect.i32(i32 %x, i32 1)
|
||
|
|
%expval = call i32 @llvm.expect.i32(i32 %x, i32 1)
|
||
|
|
ret i32 %expval
|
||
|
|
}
|
||
|
|
|
||
|
|
declare i32 @llvm.expect.i32(i32, i32) nounwind readnone
|