178 lines
3.9 KiB
LLVM
178 lines
3.9 KiB
LLVM
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -O2 -tail-dup-size=1000 -tail-dup-placement-threshold=1000 -enable-tail-merge=0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; Need to to trigger tail duplication this during
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; MachineBlockPlacement, since calls aren't tail duplicated pre-RA.
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declare void @nonconvergent_func() #0
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declare void @convergent_func() #1
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declare void @llvm.amdgcn.s.barrier() #1
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declare void @llvm.amdgcn.ds.gws.init(i32, i32) #2
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declare void @llvm.amdgcn.ds.gws.barrier(i32, i32) #2
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declare void @llvm.amdgcn.ds.gws.sema.release.all(i32 %offset) #2
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; barrier shouldn't be duplicated.
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; GCN-LABEL: {{^}}taildup_barrier:
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; GCN: s_barrier
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; GCN-NOT: s_barrier
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define void @taildup_barrier(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond) #0 {
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entry:
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br i1 %cond, label %bb1, label %bb2
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bb1:
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store i32 0, i32 addrspace(1)* %a
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br label %call
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bb2:
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store i32 1, i32 addrspace(1)* %a
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br label %call
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call:
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call void @llvm.amdgcn.s.barrier()
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}taildup_convergent_call:
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; GCN: s_swappc_b64
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; GCN-NOT: s_swappc_b64
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define void @taildup_convergent_call(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond) #1 {
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entry:
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br i1 %cond, label %bb1, label %bb2
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bb1:
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store i32 0, i32 addrspace(1)* %a
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br label %call
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bb2:
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store i32 1, i32 addrspace(1)* %a
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br label %call
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call:
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call void @convergent_func()
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br label %ret
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ret:
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ret void
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}
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; TODO: Currently there is only one convergent call pseudo, but this
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; theoretically could use a nonconvergent variant.
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; GCN-LABEL: {{^}}taildup_nonconvergent_call:
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; GCN: s_swappc_b64
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; GCN-NOT: s_swappc_b64
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define void @taildup_nonconvergent_call(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond) #1 {
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entry:
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br i1 %cond, label %bb1, label %bb2
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bb1:
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store i32 0, i32 addrspace(1)* %a
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br label %call
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bb2:
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store i32 1, i32 addrspace(1)* %a
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br label %call
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call:
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call void @nonconvergent_func()
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}taildup_convergent_tailcall:
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; GCN: s_setpc_b64
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; GCN-NOT: s_setpc_b64
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define void @taildup_convergent_tailcall(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond) #1 {
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entry:
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br i1 %cond, label %bb1, label %bb2
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bb1:
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store i32 0, i32 addrspace(1)* %a
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br label %call
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bb2:
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store i32 1, i32 addrspace(1)* %a
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br label %call
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call:
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tail call void @convergent_func()
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ret void
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}
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; GCN-LABEL: {{^}}taildup_gws_init:
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; GCN: ds_gws_init
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; GCN-NOT: ds_gws_init
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define amdgpu_kernel void @taildup_gws_init(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond, i32 %val, i32 %offset) #0 {
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entry:
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br i1 %cond, label %bb1, label %bb2
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bb1:
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store i32 0, i32 addrspace(1)* %a
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br label %call
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bb2:
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store i32 1, i32 addrspace(1)* %a
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br label %call
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call:
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call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}taildup_gws_barrier:
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; GCN: ds_gws_barrier
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; GCN-NOT: ds_gws_barrier
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define amdgpu_kernel void @taildup_gws_barrier(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond, i32 %val, i32 %offset) #0 {
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entry:
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br i1 %cond, label %bb1, label %bb2
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bb1:
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store i32 0, i32 addrspace(1)* %a
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br label %call
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bb2:
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store i32 1, i32 addrspace(1)* %a
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br label %call
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call:
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %offset)
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}taildup_gws_sema_release_all:
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; GCN: ds_gws_sema_release_all
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; GCN-NOT: ds_gws
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define amdgpu_kernel void @taildup_gws_sema_release_all(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond, i32 %offset) #0 {
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entry:
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br i1 %cond, label %bb1, label %bb2
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bb1:
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store i32 0, i32 addrspace(1)* %a
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br label %call
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bb2:
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store i32 1, i32 addrspace(1)* %a
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br label %call
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call:
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call void @llvm.amdgcn.ds.gws.sema.release.all(i32 %offset)
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br label %ret
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ret:
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind convergent }
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attributes #2 = { convergent inaccessiblememonly nounwind }
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