275 lines
10 KiB
LLVM
275 lines
10 KiB
LLVM
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s
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; FUNC-LABEL: {{^}}s_abs_i32:
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; GCN: s_abs_i32
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; GCN: s_add_i32
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; EG: MAX_INT
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define amdgpu_kernel void @s_abs_i32(i32 addrspace(1)* %out, i32 %val) nounwind {
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%neg = sub i32 0, %val
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%cond = icmp sgt i32 %val, %neg
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%res = select i1 %cond, i32 %val, i32 %neg
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%res2 = add i32 %res, 2
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store i32 %res2, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_abs_i32:
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; SIVI: v_sub_{{i|u}}32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]]
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; GFX9: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SRC:v[0-9]+]]
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; GCN: v_max_i32_e32 {{v[0-9]+}}, [[SRC]], [[NEG]]
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; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2
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; EG: MAX_INT
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define amdgpu_kernel void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds i32, i32 addrspace(1)* %src, i32 %tid
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%val = load i32, i32 addrspace(1)* %gep.in, align 4
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%neg = sub i32 0, %val
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%cond = icmp sgt i32 %val, %neg
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%res = select i1 %cond, i32 %val, i32 %neg
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%res2 = add i32 %res, 2
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store i32 %res2, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_abs_i32_repeat_user:
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; SIVI: v_sub_{{i|u}}32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]]
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; GFX9: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SRC:v[0-9]+]]
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; GCN: v_max_i32_e32 [[MAX:v[0-9]+]], [[SRC]], [[NEG]]
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; GCN: v_mul_lo_u32 v{{[0-9]+}}, [[MAX]], [[MAX]]
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define amdgpu_kernel void @v_abs_i32_repeat_user(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds i32, i32 addrspace(1)* %src, i32 %tid
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%val = load i32, i32 addrspace(1)* %gep.in, align 4
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%neg = sub i32 0, %val
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%cond = icmp sgt i32 %val, %neg
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%res = select i1 %cond, i32 %val, i32 %neg
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%mul = mul i32 %res, %res
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store i32 %mul, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_abs_v2i32:
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; GCN: s_abs_i32
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; GCN: s_abs_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; EG: MAX_INT
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; EG: MAX_INT
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define amdgpu_kernel void @s_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %val) nounwind {
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%z0 = insertelement <2 x i32> undef, i32 0, i32 0
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%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
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%t0 = insertelement <2 x i32> undef, i32 2, i32 0
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%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
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%neg = sub <2 x i32> %z1, %val
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%cond = icmp sgt <2 x i32> %val, %neg
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%res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg
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%res2 = add <2 x i32> %res, %t1
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store <2 x i32> %res2, <2 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_abs_v2i32:
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; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
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; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG0:v[0-9]+]], 0, [[SRC0:v[0-9]+]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG1:v[0-9]+]], 0, [[SRC1:v[0-9]+]]
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; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]]
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; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]]
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; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc
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; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,
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; EG: MAX_INT
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; EG: MAX_INT
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define amdgpu_kernel void @v_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %src) nounwind {
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%z0 = insertelement <2 x i32> undef, i32 0, i32 0
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%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
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%t0 = insertelement <2 x i32> undef, i32 2, i32 0
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%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %src, i32 %tid
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%val = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in, align 4
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%neg = sub <2 x i32> %z1, %val
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%cond = icmp sgt <2 x i32> %val, %neg
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%res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg
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%res2 = add <2 x i32> %res, %t1
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store <2 x i32> %res2, <2 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_abs_v4i32:
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; TODO: this should use s_abs_i32
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; GCN: s_abs_i32
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; GCN: s_abs_i32
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; GCN: s_abs_i32
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; GCN: s_abs_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; EG: MAX_INT
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; EG: MAX_INT
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; EG: MAX_INT
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; EG: MAX_INT
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define amdgpu_kernel void @s_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %val) nounwind {
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%z0 = insertelement <4 x i32> undef, i32 0, i32 0
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%z1 = insertelement <4 x i32> %z0, i32 0, i32 1
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%z2 = insertelement <4 x i32> %z1, i32 0, i32 2
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%z3 = insertelement <4 x i32> %z2, i32 0, i32 3
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%t0 = insertelement <4 x i32> undef, i32 2, i32 0
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%t1 = insertelement <4 x i32> %t0, i32 2, i32 1
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%t2 = insertelement <4 x i32> %t1, i32 2, i32 2
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%t3 = insertelement <4 x i32> %t2, i32 2, i32 3
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%neg = sub <4 x i32> %z3, %val
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%cond = icmp sgt <4 x i32> %val, %neg
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%res = select <4 x i1> %cond, <4 x i32> %val, <4 x i32> %neg
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%res2 = add <4 x i32> %res, %t3
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store <4 x i32> %res2, <4 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_abs_v4i32:
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; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
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; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
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; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]]
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; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG3:v[0-9]+]], vcc, 0, [[SRC3:v[0-9]+]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG0:v[0-9]+]], 0, [[SRC0:v[0-9]+]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG1:v[0-9]+]], 0, [[SRC1:v[0-9]+]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG2:v[0-9]+]], 0, [[SRC2:v[0-9]+]]
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; GFX9-DAG: v_sub_u32_e32 [[NEG3:v[0-9]+]], 0, [[SRC3:v[0-9]+]]
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; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]]
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; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]]
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; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC2]], [[NEG2]]
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; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC3]], [[NEG3]]
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; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc,
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; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc,
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; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc,
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; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,
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; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2,
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; EG: MAX_INT
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; EG: MAX_INT
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; EG: MAX_INT
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; EG: MAX_INT
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define amdgpu_kernel void @v_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %src) nounwind {
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%z0 = insertelement <4 x i32> undef, i32 0, i32 0
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%z1 = insertelement <4 x i32> %z0, i32 0, i32 1
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%z2 = insertelement <4 x i32> %z1, i32 0, i32 2
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%z3 = insertelement <4 x i32> %z2, i32 0, i32 3
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%t0 = insertelement <4 x i32> undef, i32 2, i32 0
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%t1 = insertelement <4 x i32> %t0, i32 2, i32 1
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%t2 = insertelement <4 x i32> %t1, i32 2, i32 2
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%t3 = insertelement <4 x i32> %t2, i32 2, i32 3
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %src, i32 %tid
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%val = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in, align 4
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%neg = sub <4 x i32> %z3, %val
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%cond = icmp sgt <4 x i32> %val, %neg
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%res = select <4 x i1> %cond, <4 x i32> %val, <4 x i32> %neg
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%res2 = add <4 x i32> %res, %t3
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store <4 x i32> %res2, <4 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_min_max_i32:
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; GCN: s_load_dword [[VAL0:s[0-9]+]]
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; GCN: s_load_dword [[VAL1:s[0-9]+]]
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; GCN-DAG: s_min_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]
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; GCN-DAG: s_max_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]]
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define amdgpu_kernel void @s_min_max_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, [8 x i32], i32 %val0, [8 x i32], i32 %val1) nounwind {
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%cond0 = icmp sgt i32 %val0, %val1
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%sel0 = select i1 %cond0, i32 %val0, i32 %val1
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%sel1 = select i1 %cond0, i32 %val1, i32 %val0
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store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
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store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_min_max_i32:
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; GCN: {{buffer|flat|global}}_load_dword [[VAL0:v[0-9]+]]
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; GCN: {{buffer|flat|global}}_load_dword [[VAL1:v[0-9]+]]
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; GCN-DAG: v_min_i32_e32 v{{[0-9]+}}, [[VAL0]], [[VAL1]]
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; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL0]], [[VAL1]]
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define amdgpu_kernel void @v_min_max_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr0, i32 addrspace(1)* %ptr1) nounwind {
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%val0 = load volatile i32, i32 addrspace(1)* %ptr0
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%val1 = load volatile i32, i32 addrspace(1)* %ptr1
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%cond0 = icmp sgt i32 %val0, %val1
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%sel0 = select i1 %cond0, i32 %val0, i32 %val1
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%sel1 = select i1 %cond0, i32 %val1, i32 %val0
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store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
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store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_min_max_v4i32:
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; GCN-DAG: s_min_i32
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; GCN-DAG: s_min_i32
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; GCN-DAG: s_min_i32
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; GCN-DAG: s_min_i32
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; GCN-DAG: s_max_i32
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; GCN-DAG: s_max_i32
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; GCN-DAG: s_max_i32
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; GCN-DAG: s_max_i32
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define amdgpu_kernel void @s_min_max_v4i32(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %out1, <4 x i32> %val0, <4 x i32> %val1) nounwind {
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%cond0 = icmp sgt <4 x i32> %val0, %val1
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%sel0 = select <4 x i1> %cond0, <4 x i32> %val0, <4 x i32> %val1
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%sel1 = select <4 x i1> %cond0, <4 x i32> %val1, <4 x i32> %val0
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store volatile <4 x i32> %sel0, <4 x i32> addrspace(1)* %out0, align 4
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store volatile <4 x i32> %sel1, <4 x i32> addrspace(1)* %out1, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_min_max_i32_user:
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; GCN: v_cmp_gt_i32_e32
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; GCN-DAG: v_cndmask_b32_e32
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||
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; GCN-DAG: v_cndmask_b32_e32
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||
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; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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|
define amdgpu_kernel void @v_min_max_i32_user(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr0, i32 addrspace(1)* %ptr1) nounwind {
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%val0 = load volatile i32, i32 addrspace(1)* %ptr0
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||
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%val1 = load volatile i32, i32 addrspace(1)* %ptr1
|
||
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|
|
||
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|
%cond0 = icmp sgt i32 %val0, %val1
|
||
|
|
%sel0 = select i1 %cond0, i32 %val0, i32 %val1
|
||
|
|
%sel1 = select i1 %cond0, i32 %val1, i32 %val0
|
||
|
|
|
||
|
|
store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4
|
||
|
|
store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4
|
||
|
|
store volatile i1 %cond0, i1 addrspace(1)* undef
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
||
|
|
|
||
|
|
attributes #0 = { nounwind readnone }
|
||
|
|
attributes #1 = { nounwind }
|