142 lines
7.0 KiB
LLVM
142 lines
7.0 KiB
LLVM
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_10,GFX10 %s
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_1:
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; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel:[0,1] op_sel_hi:[1,0]{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_0_1(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH3C00>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_0:
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; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_1_0(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH0000>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_1:
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; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel_hi:[1,0]{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_1_1(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH3C00>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_m1:
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; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0 op_sel:[0,1] op_sel_hi:[1,0]{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_0_m1(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xHBC00>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_0:
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; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_m1_0(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xH0000>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_m1:
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; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0 op_sel_hi:[1,0]{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_m1_m1(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xHBC00>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_0:
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; GFX9_10: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 0{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_0_0(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH0000>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_41c8:
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; GFX9: s_mov_b32 [[C:s[0-9]+]], 0x41c80000
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; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, [[C]]{{$}}
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; GFX10: v_pk_max_f16 v{{[0-9]+}}, 0x41c8, v{{[0-9]+}} op_sel:[1,0] op_sel_hi:[0,1]{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_0_41c8(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH41C8>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_41c8_0:
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; GFX9: s_movk_i32 [[C:s[0-9]+]], 0x41c8
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; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, [[C]]{{$}}
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; GFX10: v_pk_max_f16 v{{[0-9]+}}, 0x41c8, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_41c8_0(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH41C8, half 0xH0>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_pk_max_f16_literal_42ca_41c8:
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; GFX9: s_mov_b32 [[C:s[0-9]+]], 0x41c842ca
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; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, [[C]]{{$}}
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; GFX10: v_pk_max_f16 v{{[0-9]+}}, 0x41c842ca, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @test_pk_max_f16_literal_42ca_41c8(<2 x half> addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = zext i32 %tmp to i64
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%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
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%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
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%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH42CA, half 0xH41C8>)
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store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
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ret void
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}
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declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
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declare i32 @llvm.amdgcn.workitem.id.x()
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