83 lines
2.0 KiB
LLVM
83 lines
2.0 KiB
LLVM
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}negated_cond:
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; GCN: BB0_1:
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; GCN: v_cmp_eq_u32_e64 [[CC:[^,]+]],
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; GCN: BB0_3:
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; GCN-NOT: v_cndmask_b32
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; GCN-NOT: v_cmp
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; GCN: s_andn2_b64 vcc, exec, [[CC]]
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; GCN: s_cbranch_vccnz BB0_2
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define amdgpu_kernel void @negated_cond(i32 addrspace(1)* %arg1) {
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bb:
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br label %bb1
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bb1:
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%tmp1 = load i32, i32 addrspace(1)* %arg1
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%tmp2 = icmp eq i32 %tmp1, 0
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br label %bb2
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bb2:
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%tmp3 = phi i32 [ 0, %bb1 ], [ %tmp6, %bb4 ]
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%tmp4 = shl i32 %tmp3, 5
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br i1 %tmp2, label %bb3, label %bb4
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bb3:
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%tmp5 = add i32 %tmp4, 1
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br label %bb4
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bb4:
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%tmp6 = phi i32 [ %tmp5, %bb3 ], [ %tmp4, %bb2 ]
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tmp6
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store i32 0, i32 addrspace(1)* %gep
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%tmp7 = icmp eq i32 %tmp6, 32
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br i1 %tmp7, label %bb1, label %bb2
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}
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; GCN-LABEL: {{^}}negated_cond_dominated_blocks:
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; GCN: v_cmp_ne_u32_e64 [[CC1:[^,]+]],
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; GCN: s_branch [[BB1:BB[0-9]+_[0-9]+]]
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; GCN: [[BB0:BB[0-9]+_[0-9]+]]
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; GCN-NOT: v_cndmask_b32
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; GCN-NOT: v_cmp
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; GCN: [[BB1]]:
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; GCN: s_mov_b64 [[CC2:[^,]+]], -1
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; GCN: s_mov_b64 vcc, [[CC1]]
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; GCN: s_cbranch_vccz [[BB2:BB[0-9]+_[0-9]+]]
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; GCN: s_mov_b64 [[CC2]], 0
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; GCN: [[BB2]]:
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; GCN: s_andn2_b64 vcc, exec, [[CC2]]
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; GCN: s_cbranch_vccnz [[BB0]]
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define amdgpu_kernel void @negated_cond_dominated_blocks(i32 addrspace(1)* %arg1) {
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bb:
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br label %bb2
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bb2:
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%tmp1 = load i32, i32 addrspace(1)* %arg1
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%tmp2 = icmp eq i32 %tmp1, 0
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br label %bb4
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bb3:
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ret void
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bb4:
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%tmp3 = phi i32 [ 0, %bb2 ], [ %tmp7, %bb7 ]
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%tmp4 = shl i32 %tmp3, 5
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br i1 %tmp2, label %bb5, label %bb6
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bb5:
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%tmp5 = add i32 %tmp4, 1
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br label %bb7
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bb6:
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%tmp6 = add i32 %tmp3, 1
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br label %bb7
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bb7:
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%tmp7 = phi i32 [ %tmp5, %bb5 ], [ %tmp6, %bb6 ]
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tmp7
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store i32 0, i32 addrspace(1)* %gep
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%tmp8 = icmp eq i32 %tmp7, 32
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br i1 %tmp8, label %bb3, label %bb4
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}
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