147 lines
5.2 KiB
LLVM
147 lines
5.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-- -mcpu=pitcairn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @zext_shl64_to_32(i64 addrspace(1)* nocapture %out, i32 %x) {
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; GCN-LABEL: zext_shl64_to_32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_lshl_b32 s0, s0, 2
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%and = and i32 %x, 1073741823
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%ext = zext i32 %and to i64
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%shl = shl i64 %ext, 2
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store i64 %shl, i64 addrspace(1)* %out, align 4
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ret void
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}
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define amdgpu_kernel void @sext_shl64_to_32(i64 addrspace(1)* nocapture %out, i32 %x) {
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; GCN-LABEL: sext_shl64_to_32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_and_b32 s0, s0, 0x1fffffff
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; GCN-NEXT: s_lshl_b32 s0, s0, 2
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%and = and i32 %x, 536870911
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%ext = sext i32 %and to i64
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%shl = shl i64 %ext, 2
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store i64 %shl, i64 addrspace(1)* %out, align 4
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ret void
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}
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define amdgpu_kernel void @zext_shl64_overflow(i64 addrspace(1)* nocapture %out, i32 %x) {
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; GCN-LABEL: zext_shl64_overflow:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
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; GCN-NEXT: s_mov_b32 s1, 0
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_bitset0_b32 s0, 31
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; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%and = and i32 %x, 2147483647
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%ext = zext i32 %and to i64
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%shl = shl i64 %ext, 2
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store i64 %shl, i64 addrspace(1)* %out, align 4
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ret void
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}
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define amdgpu_kernel void @sext_shl64_overflow(i64 addrspace(1)* nocapture %out, i32 %x) {
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; GCN-LABEL: sext_shl64_overflow:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; GCN-NEXT: s_load_dword s0, s[0:1], 0xb
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; GCN-NEXT: s_mov_b32 s1, 0
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_bitset0_b32 s0, 31
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; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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%and = and i32 %x, 2147483647
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%ext = sext i32 %and to i64
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%shl = shl i64 %ext, 2
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store i64 %shl, i64 addrspace(1)* %out, align 4
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ret void
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}
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define amdgpu_kernel void @mulu24_shl64(i32 addrspace(1)* nocapture %arg) {
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; GCN-LABEL: mulu24_shl64:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-NEXT: v_and_b32_e32 v0, 6, v0
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; GCN-NEXT: v_mul_u32_u24_e32 v0, 7, v0
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_store_dword v1, v[0:1], s[0:3], 0 addr64
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; GCN-NEXT: s_endpgm
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = and i32 %tmp, 6
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%mulconv = mul nuw nsw i32 %tmp1, 7
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%tmp2 = zext i32 %mulconv to i64
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%tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp2
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store i32 0, i32 addrspace(1)* %tmp3, align 4
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ret void
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}
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define amdgpu_kernel void @muli24_shl64(i64 addrspace(1)* nocapture %arg, i32 addrspace(1)* nocapture readonly %arg1) {
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; GCN-LABEL: muli24_shl64:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[0:1], s[6:7]
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; GCN-NEXT: buffer_load_dword v1, v[1:2], s[0:3], 0 addr64
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; GCN-NEXT: v_lshlrev_b32_e32 v3, 3, v0
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; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
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; GCN-NEXT: v_mov_b32_e32 v4, v2
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_or_b32_e32 v0, 0x800000, v1
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; GCN-NEXT: v_mul_i32_i24_e32 v0, -7, v0
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; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v0
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; GCN-NEXT: buffer_store_dwordx2 v[1:2], v[3:4], s[4:7], 0 addr64
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; GCN-NEXT: s_endpgm
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = sext i32 %tmp to i64
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%tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp2
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%tmp4 = load i32, i32 addrspace(1)* %tmp3, align 4
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%tmp5 = or i32 %tmp4, -8388608
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%tmp6 = mul nsw i32 %tmp5, -7
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%tmp7 = zext i32 %tmp6 to i64
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%tmp8 = shl nuw nsw i64 %tmp7, 3
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%tmp9 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp2
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store i64 %tmp8, i64 addrspace(1)* %tmp9, align 8
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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