115 lines
5.1 KiB
LLVM
115 lines
5.1 KiB
LLVM
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;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=VERDE %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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;CHECK-LABEL: {{^}}buffer_store:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
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;CHECK: buffer_store_format_xyzw v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
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;CHECK: buffer_store_format_xyzw v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
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define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_immoffs:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
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define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_idx:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_ofs:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
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define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_both:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
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define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_both_reversed:
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;CHECK: v_mov_b32_e32 v6, v4
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
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define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i32 0, i32 0)
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ret void
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}
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; Ideally, the register allocator would avoid the wait here
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;
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;CHECK-LABEL: {{^}}buffer_store_wait:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
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;VERDE: s_waitcnt expcnt(0)
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;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0)
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i32 0, i32 0)
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call void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x1:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x1_i32:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_store_x1_i32(<4 x i32> inreg %rsrc, i32 %data, i32 %index) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.i32(i32 %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_x2:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.struct.buffer.store.format.f32(float, <4 x i32>, i32, i32, i32, i32) #0
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declare void @llvm.amdgcn.struct.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32) #0
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declare void @llvm.amdgcn.struct.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32) #0
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declare void @llvm.amdgcn.struct.buffer.store.format.i32(i32, <4 x i32>, i32, i32, i32, i32) #0
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declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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