65 lines
2.3 KiB
LLVM
65 lines
2.3 KiB
LLVM
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}test1:
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; CHECK: s_mov_b64 s[0:1], exec
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; CHECK: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
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;
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; Note: The hardware doesn't implement EXEC as src2 for v_cndmask.
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;
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; Note: We could generate better code here if we recognized earlier that
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; there is no WQM use and therefore llvm.amdgcn.ps.live is constant. However,
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; the expectation is that the intrinsic will be used in non-trivial shaders,
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; so such an optimization doesn't seem worth the effort.
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define amdgpu_ps float @test1() #0 {
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%live = call i1 @llvm.amdgcn.ps.live()
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%live.32 = zext i1 %live to i32
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%r = bitcast i32 %live.32 to float
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ret float %r
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}
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; CHECK-LABEL: {{^}}test2:
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; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
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; Following copy should go away:
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; CHECK: s_mov_b64 [[COPY:s\[[0-9]+:[0-9]+\]]], [[LIVE]]
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; CHECK-DAG: s_wqm_b64 exec, exec
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; CHECK-DAG: v_cndmask_b32_e64 [[VAR:v[0-9]+]], 0, 1, [[COPY]]
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; CHECK: image_sample v0, [[VAR]],
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define amdgpu_ps float @test2() #0 {
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%live = call i1 @llvm.amdgcn.ps.live()
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%live.32 = zext i1 %live to i32
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%live.32.bc = bitcast i32 %live.32 to float
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%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %live.32.bc, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%r = extractelement <4 x float> %t, i32 0
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ret float %r
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}
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; CHECK-LABEL: {{^}}test3:
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; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
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; CHECK-DAG: s_wqm_b64 exec, exec
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; CHECK-DAG: s_xor_b64 [[HELPER:s\[[0-9]+:[0-9]+\]]], [[LIVE]], -1
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; CHECK_DAG: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[HELPER]]
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; CHECK: ; %dead
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define amdgpu_ps float @test3(i32 %in) #0 {
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entry:
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%live = call i1 @llvm.amdgcn.ps.live()
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br i1 %live, label %end, label %dead
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dead:
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%tc.dead = mul i32 %in, 2
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br label %end
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end:
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%tc = phi i32 [ %in, %entry ], [ %tc.dead, %dead ]
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%tc.bc = bitcast i32 %tc to float
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%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tc.bc, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0
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%r = extractelement <4 x float> %t, i32 0
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ret float %r
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}
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declare i1 @llvm.amdgcn.ps.live() #1
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declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readonly }
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