188 lines
8.9 KiB
LLVM
188 lines
8.9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-32BANK %s
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; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-32BANK %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-16BANK %s
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define amdgpu_ps half @interp_f16(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
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; GFX9-32BANK-LABEL: interp_f16:
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; GFX9-32BANK: ; %bb.0: ; %main_body
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; GFX9-32BANK-NEXT: s_mov_b32 m0, s2
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; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v1, v0, attr2.y
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; GFX9-32BANK-NEXT: v_mov_b32_e32 v2, s1
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; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high
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; GFX9-32BANK-NEXT: v_interp_p2_legacy_f16 v1, v2, attr2.y, v1
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; GFX9-32BANK-NEXT: v_interp_p2_legacy_f16 v0, v2, attr2.y, v0 high
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
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; GFX9-32BANK-NEXT: v_add_f16_e32 v0, v1, v0
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; GFX9-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-32BANK-LABEL: interp_f16:
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; GFX8-32BANK: ; %bb.0: ; %main_body
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; GFX8-32BANK-NEXT: s_mov_b32 m0, s2
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; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v1, v0, attr2.y
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; GFX8-32BANK-NEXT: v_mov_b32_e32 v2, s1
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; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high
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; GFX8-32BANK-NEXT: v_interp_p2_f16 v1, v2, attr2.y, v1
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; GFX8-32BANK-NEXT: v_interp_p2_f16 v0, v2, attr2.y, v0 high
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
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; GFX8-32BANK-NEXT: v_add_f16_e32 v0, v1, v0
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; GFX8-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-16BANK-LABEL: interp_f16:
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; GFX8-16BANK: ; %bb.0: ; %main_body
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; GFX8-16BANK-NEXT: s_mov_b32 m0, s2
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; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v0, p0, attr2.y
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; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s0
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v2, v1, attr2.y, v0
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; GFX8-16BANK-NEXT: v_mov_b32_e32 v3, s1
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; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v1, attr2.y, v0 high
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; GFX8-16BANK-NEXT: v_interp_p2_f16 v2, v3, attr2.y, v2
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; GFX8-16BANK-NEXT: v_interp_p2_f16 v0, v3, attr2.y, v0 high
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
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; GFX8-16BANK-NEXT: v_add_f16_e32 v0, v2, v0
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; GFX8-16BANK-NEXT: ; return to shader part epilog
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main_body:
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%p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)
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%p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)
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%p1_1 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 1, i32 %m0)
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%p2_1 = call half @llvm.amdgcn.interp.p2.f16(float %p1_1, float %j, i32 1, i32 2, i1 1, i32 %m0)
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%res = fadd half %p2_0, %p2_1
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ret half %res
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}
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; check that m0 is setup correctly before the interp p1 instruction
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define amdgpu_ps half @interp_p1_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
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; GFX9-32BANK-LABEL: interp_p1_m0_setup:
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; GFX9-32BANK: ; %bb.0: ; %main_body
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; GFX9-32BANK-NEXT: ;;#ASMSTART
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; GFX9-32BANK-NEXT: s_mov_b32 m0, 0
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; GFX9-32BANK-NEXT: ;;#ASMEND
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; GFX9-32BANK-NEXT: s_mov_b32 s3, m0
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; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-32BANK-NEXT: s_mov_b32 m0, s2
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
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; GFX9-32BANK-NEXT: v_mov_b32_e32 v1, s1
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; GFX9-32BANK-NEXT: v_interp_p2_legacy_f16 v0, v1, attr2.y, v0
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
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; GFX9-32BANK-NEXT: v_add_f16_e32 v0, s3, v0
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; GFX9-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-32BANK-LABEL: interp_p1_m0_setup:
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; GFX8-32BANK: ; %bb.0: ; %main_body
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; GFX8-32BANK-NEXT: ;;#ASMSTART
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; GFX8-32BANK-NEXT: s_mov_b32 m0, 0
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; GFX8-32BANK-NEXT: ;;#ASMEND
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; GFX8-32BANK-NEXT: s_mov_b32 s3, m0
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; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-32BANK-NEXT: s_mov_b32 m0, s2
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
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; GFX8-32BANK-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-32BANK-NEXT: v_interp_p2_f16 v0, v1, attr2.y, v0
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
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; GFX8-32BANK-NEXT: v_add_f16_e32 v0, s3, v0
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; GFX8-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-16BANK-LABEL: interp_p1_m0_setup:
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; GFX8-16BANK: ; %bb.0: ; %main_body
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; GFX8-16BANK-NEXT: ;;#ASMSTART
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; GFX8-16BANK-NEXT: s_mov_b32 m0, 0
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; GFX8-16BANK-NEXT: ;;#ASMEND
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; GFX8-16BANK-NEXT: s_mov_b32 s3, m0
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; GFX8-16BANK-NEXT: s_mov_b32 m0, s2
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; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v0, p0, attr2.y
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; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s0
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v1, attr2.y, v0
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; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-16BANK-NEXT: v_interp_p2_f16 v0, v1, attr2.y, v0
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
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; GFX8-16BANK-NEXT: v_add_f16_e32 v0, s3, v0
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; GFX8-16BANK-NEXT: ; return to shader part epilog
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main_body:
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%mx = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
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%p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)
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%p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)
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%my = trunc i32 %mx to i16
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%mh = bitcast i16 %my to half
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%res = fadd half %p2_0, %mh
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ret half %res
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}
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; check that m0 is setup correctly before the interp p2 instruction
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define amdgpu_ps half @interp_p2_m0_setup(float inreg %i, float inreg %j, i32 inreg %m0) #0 {
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; GFX9-32BANK-LABEL: interp_p2_m0_setup:
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; GFX9-32BANK: ; %bb.0: ; %main_body
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; GFX9-32BANK-NEXT: s_mov_b32 m0, s2
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; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
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; GFX9-32BANK-NEXT: ;;#ASMSTART
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; GFX9-32BANK-NEXT: s_mov_b32 m0, 0
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; GFX9-32BANK-NEXT: ;;#ASMEND
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; GFX9-32BANK-NEXT: s_mov_b32 s0, m0
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; GFX9-32BANK-NEXT: v_mov_b32_e32 v1, s1
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; GFX9-32BANK-NEXT: s_mov_b32 m0, s2
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; GFX9-32BANK-NEXT: v_interp_p2_legacy_f16 v0, v1, attr2.y, v0
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
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; GFX9-32BANK-NEXT: v_add_f16_e32 v0, s0, v0
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; GFX9-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-32BANK-LABEL: interp_p2_m0_setup:
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; GFX8-32BANK: ; %bb.0: ; %main_body
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; GFX8-32BANK-NEXT: s_mov_b32 m0, s2
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; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
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; GFX8-32BANK-NEXT: ;;#ASMSTART
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; GFX8-32BANK-NEXT: s_mov_b32 m0, 0
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; GFX8-32BANK-NEXT: ;;#ASMEND
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; GFX8-32BANK-NEXT: s_mov_b32 s0, m0
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; GFX8-32BANK-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-32BANK-NEXT: s_mov_b32 m0, s2
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; GFX8-32BANK-NEXT: v_interp_p2_f16 v0, v1, attr2.y, v0
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
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; GFX8-32BANK-NEXT: v_add_f16_e32 v0, s0, v0
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; GFX8-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-16BANK-LABEL: interp_p2_m0_setup:
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; GFX8-16BANK: ; %bb.0: ; %main_body
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; GFX8-16BANK-NEXT: s_mov_b32 m0, s2
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; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v0, p0, attr2.y
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; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s0
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v1, attr2.y, v0
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; GFX8-16BANK-NEXT: ;;#ASMSTART
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; GFX8-16BANK-NEXT: s_mov_b32 m0, 0
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; GFX8-16BANK-NEXT: ;;#ASMEND
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; GFX8-16BANK-NEXT: s_mov_b32 s0, m0
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; GFX8-16BANK-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-16BANK-NEXT: s_mov_b32 m0, s2
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; GFX8-16BANK-NEXT: v_interp_p2_f16 v0, v1, attr2.y, v0
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
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; GFX8-16BANK-NEXT: v_add_f16_e32 v0, s0, v0
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; GFX8-16BANK-NEXT: ; return to shader part epilog
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main_body:
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%p1_0 = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 0, i32 %m0)
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%mx = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
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%p2_0 = call half @llvm.amdgcn.interp.p2.f16(float %p1_0, float %j, i32 1, i32 2, i1 0, i32 %m0)
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%my = trunc i32 %mx to i16
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%mh = bitcast i16 %my to half
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%res = fadd half %p2_0, %mh
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ret half %res
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}
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; float @llvm.amdgcn.interp.p1.f16(i, attrchan, attr, high, m0)
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declare float @llvm.amdgcn.interp.p1.f16(float, i32, i32, i1, i32) #0
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; half @llvm.amdgcn.interp.p1.f16(p1, j, attrchan, attr, high, m0)
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declare half @llvm.amdgcn.interp.p2.f16(float, float, i32, i32, i1, i32) #0
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declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #0
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attributes #0 = { nounwind readnone }
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