237 lines
9.0 KiB
LLVM
237 lines
9.0 KiB
LLVM
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefixes=CHECK,CIVI %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,CIVI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,CIVI,CIVI-HSA %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,GFX10 %s
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; CHECK-LABEL: {{^}}store_flat_i32:
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; CHECK-DAG: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]],
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; CHECK-DAG: s_load_dword s[[SDATA:[0-9]+]],
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; CHECK: s_waitcnt lgkmcnt(0)
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; CHECK-DAG: v_mov_b32_e32 v[[DATA:[0-9]+]], s[[SDATA]]
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; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
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; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
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; CHECK: flat_store_dword v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}, v[[DATA]]
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define amdgpu_kernel void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 {
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%fptr = addrspacecast i32 addrspace(1)* %gptr to i32*
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store volatile i32 %x, i32* %fptr, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_i64:
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; CHECK: flat_store_dwordx2
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define amdgpu_kernel void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 {
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%fptr = addrspacecast i64 addrspace(1)* %gptr to i64*
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store volatile i64 %x, i64* %fptr, align 8
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_v4i32:
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; CHECK: flat_store_dwordx4
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define amdgpu_kernel void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 {
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%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32>*
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store volatile <4 x i32> %x, <4 x i32>* %fptr, align 16
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_trunc_i16:
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; CHECK: flat_store_short
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define amdgpu_kernel void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 {
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%fptr = addrspacecast i16 addrspace(1)* %gptr to i16*
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%y = trunc i32 %x to i16
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store volatile i16 %y, i16* %fptr, align 2
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_trunc_i8:
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; CHECK: flat_store_byte
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define amdgpu_kernel void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 {
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%fptr = addrspacecast i8 addrspace(1)* %gptr to i8*
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%y = trunc i32 %x to i8
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store volatile i8 %y, i8* %fptr, align 2
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ret void
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}
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; CHECK-LABEL: load_flat_i32:
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; CHECK: flat_load_dword
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define amdgpu_kernel void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i32 addrspace(1)* %gptr to i32*
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%fload = load volatile i32, i32* %fptr, align 4
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store i32 %fload, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: load_flat_i64:
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; CHECK: flat_load_dwordx2
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define amdgpu_kernel void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i64 addrspace(1)* %gptr to i64*
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%fload = load volatile i64, i64* %fptr, align 8
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store i64 %fload, i64 addrspace(1)* %out, align 8
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ret void
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}
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; CHECK-LABEL: load_flat_v4i32:
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; CHECK: flat_load_dwordx4
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define amdgpu_kernel void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32>*
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%fload = load volatile <4 x i32>, <4 x i32>* %fptr, align 32
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store <4 x i32> %fload, <4 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; CHECK-LABEL: sextload_flat_i8:
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; CHECK: flat_load_sbyte
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define amdgpu_kernel void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i8 addrspace(1)* %gptr to i8*
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%fload = load volatile i8, i8* %fptr, align 4
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%ext = sext i8 %fload to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: zextload_flat_i8:
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; CHECK: flat_load_ubyte
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define amdgpu_kernel void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i8 addrspace(1)* %gptr to i8*
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%fload = load volatile i8, i8* %fptr, align 4
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%ext = zext i8 %fload to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: sextload_flat_i16:
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; CHECK: flat_load_sshort
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define amdgpu_kernel void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i16 addrspace(1)* %gptr to i16*
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%fload = load volatile i16, i16* %fptr, align 4
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%ext = sext i16 %fload to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: zextload_flat_i16:
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; CHECK: flat_load_ushort
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define amdgpu_kernel void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
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%fptr = addrspacecast i16 addrspace(1)* %gptr to i16*
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%fload = load volatile i16, i16* %fptr, align 4
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%ext = zext i16 %fload to i32
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store i32 %ext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: flat_scratch_unaligned_load:
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; CHECK: flat_load_ubyte
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; CHECK: flat_load_ubyte
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; CHECK: flat_load_ubyte
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; CHECK: flat_load_ubyte
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define amdgpu_kernel void @flat_scratch_unaligned_load() {
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%scratch = alloca i32, addrspace(5)
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%fptr = addrspacecast i32 addrspace(5)* %scratch to i32*
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%ld = load volatile i32, i32* %fptr, align 1
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ret void
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}
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; CHECK-LABEL: flat_scratch_unaligned_store:
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; CHECK: flat_store_byte
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; CHECK: flat_store_byte
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; CHECK: flat_store_byte
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; CHECK: flat_store_byte
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define amdgpu_kernel void @flat_scratch_unaligned_store() {
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%scratch = alloca i32, addrspace(5)
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%fptr = addrspacecast i32 addrspace(5)* %scratch to i32*
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store volatile i32 0, i32* %fptr, align 1
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ret void
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}
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; CHECK-LABEL: flat_scratch_multidword_load:
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; CIVI-HSA: flat_load_dword v
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; CIVI-HSA: flat_load_dword v
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; GFX9: flat_load_dwordx2
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; GFX10: flat_load_dwordx2
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; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
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define amdgpu_kernel void @flat_scratch_multidword_load() {
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%scratch = alloca <2 x i32>, addrspace(5)
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%fptr = addrspacecast <2 x i32> addrspace(5)* %scratch to <2 x i32>*
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%ld = load volatile <2 x i32>, <2 x i32>* %fptr
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ret void
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}
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; CHECK-LABEL: flat_scratch_multidword_store:
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; CIVI-HSA: flat_store_dword v
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; CIVI-HSA: flat_store_dword v
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; GFX9: flat_store_dwordx2
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; GFX10: flat_store_dwordx2
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; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
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define amdgpu_kernel void @flat_scratch_multidword_store() {
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%scratch = alloca <2 x i32>, addrspace(5)
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%fptr = addrspacecast <2 x i32> addrspace(5)* %scratch to <2 x i32>*
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store volatile <2 x i32> zeroinitializer, <2 x i32>* %fptr
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_i8_max_offset:
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; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
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; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:4095{{$}}
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define amdgpu_kernel void @store_flat_i8_max_offset(i8* %fptr, i8 %x) #0 {
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%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4095
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store volatile i8 %x, i8* %fptr.offset
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_i8_max_offset_p1:
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; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @store_flat_i8_max_offset_p1(i8* %fptr, i8 %x) #0 {
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%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4096
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store volatile i8 %x, i8* %fptr.offset
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ret void
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}
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; CHECK-LABEL: {{^}}store_flat_i8_neg_offset:
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; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
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; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, -1,
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; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @store_flat_i8_neg_offset(i8* %fptr, i8 %x) #0 {
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%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2
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store volatile i8 %x, i8* %fptr.offset
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ret void
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}
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; CHECK-LABEL: {{^}}load_flat_i8_max_offset:
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; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095 glc{{$}}
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; GFX10: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}
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define amdgpu_kernel void @load_flat_i8_max_offset(i8* %fptr) #0 {
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%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4095
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%val = load volatile i8, i8* %fptr.offset
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ret void
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}
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; CHECK-LABEL: {{^}}load_flat_i8_max_offset_p1:
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; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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; GFX10: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}
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define amdgpu_kernel void @load_flat_i8_max_offset_p1(i8* %fptr) #0 {
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%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4096
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%val = load volatile i8, i8* %fptr.offset
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ret void
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}
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; CHECK-LABEL: {{^}}load_flat_i8_neg_offset:
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; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, -1,
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; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
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define amdgpu_kernel void @load_flat_i8_neg_offset(i8* %fptr) #0 {
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%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2
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%val = load volatile i8, i8* %fptr.offset
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind convergent }
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