84 lines
3.1 KiB
LLVM
84 lines
3.1 KiB
LLVM
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.fabs.f32(float) #1
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declare float @llvm.floor.f32(float) #1
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; FUNC-LABEL: {{^}}cvt_rpi_i32_f32:
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; SI-SAFE-NOT: v_cvt_rpi_i32_f32
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; SI-NONAN: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; SI: s_endpgm
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define amdgpu_kernel void @cvt_rpi_i32_f32(i32 addrspace(1)* %out, float %x) #0 {
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%fadd = fadd float %x, 0.5
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%floor = call float @llvm.floor.f32(float %fadd) #1
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%cvt = fptosi float %floor to i32
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store i32 %cvt, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs:
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; SI-SAFE-NOT: v_cvt_rpi_i32_f32
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; SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
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; SI: s_endpgm
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define amdgpu_kernel void @cvt_rpi_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
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%x.fabs = call float @llvm.fabs.f32(float %x) #1
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%fadd = fadd float %x.fabs, 0.5
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%floor = call float @llvm.floor.f32(float %fadd) #1
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%cvt = fptosi float %floor to i32
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store i32 %cvt, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: This doesn't work because it forms fsub 0.5, x
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; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg:
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; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
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; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}}
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
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; SI: s_endpgm
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define amdgpu_kernel void @cvt_rpi_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
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%x.fneg = fsub float -0.000000e+00, %x
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%fadd = fadd float %x.fneg, 0.5
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%floor = call float @llvm.floor.f32(float %fadd) #1
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%cvt = fptosi float %floor to i32
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store i32 %cvt, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: This doesn't work for same reason as above
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; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg:
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; SI-SAFE-NOT: v_cvt_rpi_i32_f32
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; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
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; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}|
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; SI-SAFE-NOT: v_cvt_flr_i32_f32
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; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
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; SI: s_endpgm
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define amdgpu_kernel void @cvt_rpi_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
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%x.fabs = call float @llvm.fabs.f32(float %x) #1
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%x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
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%fadd = fadd float %x.fabs.fneg, 0.5
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%floor = call float @llvm.floor.f32(float %fadd) #1
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%cvt = fptosi float %floor to i32
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store i32 %cvt, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}no_cvt_rpi_i32_f32_0:
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; SI-NOT: v_cvt_rpi_i32_f32
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; SI: v_add_f32
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; SI: v_floor_f32
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; SI: v_cvt_u32_f32
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; SI: s_endpgm
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define amdgpu_kernel void @no_cvt_rpi_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
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%fadd = fadd float %x, 0.5
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%floor = call float @llvm.floor.f32(float %fadd) #1
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%cvt = fptoui float %floor to i32
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store i32 %cvt, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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