245 lines
5.5 KiB
LLVM
245 lines
5.5 KiB
LLVM
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; RUN: llc -march=r600 -mcpu=redwood -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
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; RUN: FileCheck --check-prefix=BUG64 %s < %t
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; RUN: llc -march=r600 -mcpu=sumo -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
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; RUN: FileCheck --check-prefix=BUG64 %s < %t
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; RUN: llc -march=r600 -mcpu=barts -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
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; RUN: FileCheck --check-prefix=BUG64 %s < %t
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; RUN: llc -march=r600 -mcpu=turks -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
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; RUN: FileCheck --check-prefix=BUG64 %s < %t
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; RUN: llc -march=r600 -mcpu=caicos -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
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; RUN: FileCheck --check-prefix=BUG64 %s < %t
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; RUN: llc -march=r600 -mcpu=cedar -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
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; RUN: FileCheck --check-prefix=BUG32 %s < %t
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; RUN: llc -march=r600 -mcpu=juniper -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
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; RUN: FileCheck --check-prefix=NOBUG %s < %t
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; RUN: llc -march=r600 -mcpu=cypress -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
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; RUN: FileCheck --check-prefix=NOBUG %s < %t
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; RUN: llc -march=r600 -mcpu=cayman -debug-only=r600cf %s -o - 2>%t | FileCheck %s --check-prefix=FUNC
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; RUN: FileCheck --check-prefix=NOBUG %s < %t
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; REQUIRES: asserts
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; We are currently allocating 2 extra sub-entries on Evergreen / NI for
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; non-WQM push instructions if we change this to 1, then we will need to
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; add one level of depth to each of these tests.
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; BUG64-NOT: Applying bug work-around
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; BUG32-NOT: Applying bug work-around
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; NOBUG-NOT: Applying bug work-around
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; FUNC-LABEL: {{^}}nested3:
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define amdgpu_kernel void @nested3(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%0 = icmp sgt i32 %cond, 0
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br i1 %0, label %if.1, label %end
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if.1:
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%1 = icmp sgt i32 %cond, 10
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br i1 %1, label %if.2, label %if.store.1
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if.store.1:
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store i32 1, i32 addrspace(1)* %out
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br label %end
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if.2:
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%2 = icmp sgt i32 %cond, 20
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br i1 %2, label %if.3, label %if.2.store
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if.2.store:
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store i32 2, i32 addrspace(1)* %out
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br label %end
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if.3:
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store i32 3, i32 addrspace(1)* %out
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br label %end
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end:
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ret void
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}
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; BUG64: Applying bug work-around
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; BUG32-NOT: Applying bug work-around
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; NOBUG-NOT: Applying bug work-around
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; FUNC-LABEL: {{^}}nested4:
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define amdgpu_kernel void @nested4(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%0 = icmp sgt i32 %cond, 0
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br i1 %0, label %if.1, label %end
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if.1:
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%1 = icmp sgt i32 %cond, 10
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br i1 %1, label %if.2, label %if.1.store
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if.1.store:
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store i32 1, i32 addrspace(1)* %out
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br label %end
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if.2:
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%2 = icmp sgt i32 %cond, 20
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br i1 %2, label %if.3, label %if.2.store
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if.2.store:
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store i32 2, i32 addrspace(1)* %out
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br label %end
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if.3:
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%3 = icmp sgt i32 %cond, 30
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br i1 %3, label %if.4, label %if.3.store
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if.3.store:
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store i32 3, i32 addrspace(1)* %out
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br label %end
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if.4:
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store i32 4, i32 addrspace(1)* %out
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br label %end
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end:
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ret void
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}
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; BUG64: Applying bug work-around
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; BUG32-NOT: Applying bug work-around
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; NOBUG-NOT: Applying bug work-around
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; FUNC-LABEL: {{^}}nested7:
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define amdgpu_kernel void @nested7(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%0 = icmp sgt i32 %cond, 0
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br i1 %0, label %if.1, label %end
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if.1:
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%1 = icmp sgt i32 %cond, 10
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br i1 %1, label %if.2, label %if.1.store
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if.1.store:
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store i32 1, i32 addrspace(1)* %out
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br label %end
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if.2:
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%2 = icmp sgt i32 %cond, 20
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br i1 %2, label %if.3, label %if.2.store
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if.2.store:
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store i32 2, i32 addrspace(1)* %out
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br label %end
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if.3:
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%3 = icmp sgt i32 %cond, 30
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br i1 %3, label %if.4, label %if.3.store
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if.3.store:
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store i32 3, i32 addrspace(1)* %out
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br label %end
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if.4:
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%4 = icmp sgt i32 %cond, 40
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br i1 %4, label %if.5, label %if.4.store
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if.4.store:
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store i32 4, i32 addrspace(1)* %out
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br label %end
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if.5:
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%5 = icmp sgt i32 %cond, 50
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br i1 %5, label %if.6, label %if.5.store
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if.5.store:
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store i32 5, i32 addrspace(1)* %out
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br label %end
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if.6:
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%6 = icmp sgt i32 %cond, 60
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br i1 %6, label %if.7, label %if.6.store
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if.6.store:
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store i32 6, i32 addrspace(1)* %out
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br label %end
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if.7:
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store i32 7, i32 addrspace(1)* %out
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br label %end
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end:
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ret void
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}
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; BUG64: Applying bug work-around
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; BUG32: Applying bug work-around
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; NOBUG-NOT: Applying bug work-around
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; FUNC-LABEL: {{^}}nested8:
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define amdgpu_kernel void @nested8(i32 addrspace(1)* %out, i32 %cond) {
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entry:
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%0 = icmp sgt i32 %cond, 0
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br i1 %0, label %if.1, label %end
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if.1:
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%1 = icmp sgt i32 %cond, 10
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br i1 %1, label %if.2, label %if.1.store
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if.1.store:
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store i32 1, i32 addrspace(1)* %out
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br label %end
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if.2:
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%2 = icmp sgt i32 %cond, 20
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br i1 %2, label %if.3, label %if.2.store
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if.2.store:
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store i32 2, i32 addrspace(1)* %out
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br label %end
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if.3:
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%3 = icmp sgt i32 %cond, 30
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br i1 %3, label %if.4, label %if.3.store
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if.3.store:
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store i32 3, i32 addrspace(1)* %out
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br label %end
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if.4:
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%4 = icmp sgt i32 %cond, 40
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br i1 %4, label %if.5, label %if.4.store
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if.4.store:
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store i32 4, i32 addrspace(1)* %out
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br label %end
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if.5:
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%5 = icmp sgt i32 %cond, 50
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br i1 %5, label %if.6, label %if.5.store
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if.5.store:
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store i32 5, i32 addrspace(1)* %out
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br label %end
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if.6:
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%6 = icmp sgt i32 %cond, 60
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br i1 %6, label %if.7, label %if.6.store
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if.6.store:
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store i32 6, i32 addrspace(1)* %out
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br label %end
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if.7:
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%7 = icmp sgt i32 %cond, 70
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br i1 %7, label %if.8, label %if.7.store
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if.7.store:
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store i32 7, i32 addrspace(1)* %out
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br label %end
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if.8:
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store i32 8, i32 addrspace(1)* %out
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br label %end
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end:
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ret void
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}
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