168 lines
8.0 KiB
LLVM
168 lines
8.0 KiB
LLVM
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GFX9 %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s
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; FIXME: Should be same on CI/VI
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; GCN-LABEL: {{^}}s_ashr_v2i16:
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; GFX9: s_load_dword [[LHS:s[0-9]+]]
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; GFX9: s_load_dword [[RHS:s[0-9]+]]
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; GFX9: v_mov_b32_e32 [[VLHS:v[0-9]+]], [[LHS]]
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; GFX9: v_pk_ashrrev_i16 [[RESULT:v[0-9]+]], [[RHS]], [[VLHS]]
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; CIVI: s_load_dword [[LHS:s[0-9]+]]
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; CIVI: s_load_dword [[RHS:s[0-9]+]]
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; CIVI-DAG: s_ashr_i32
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; CIVI-DAG: s_ashr_i32
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; CIVI-DAG: s_sext_i32_i16
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; CIVI-DAG: s_sext_i32_i16
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; CIVI-DAG: s_ashr_i32
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; CIVI-DAG: s_ashr_i32
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; CIVI-DAG: s_lshl_b32
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; CIVI: s_and_b32
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; CIVI: s_or_b32
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define amdgpu_kernel void @s_ashr_v2i16(<2 x i16> addrspace(1)* %out, i32, <2 x i16> %lhs, i32, <2 x i16> %rhs) #0 {
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%result = ashr <2 x i16> %lhs, %rhs
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store <2 x i16> %result, <2 x i16> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_ashr_v2i16:
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; GCN: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
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; GCN: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
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; GFX9: v_pk_ashrrev_i16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
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; VI: v_ashrrev_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; CI: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}}
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; CI-DAG: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], [[RHS]]
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; CI-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16
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; CI: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, [[LHS]]
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; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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; CI: v_ashr_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; CI: v_ashr_i32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
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; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_ashr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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%b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
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%a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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%b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
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%result = ashr <2 x i16> %a, %b
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store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}ashr_v_s_v2i16:
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; GFX9: s_load_dword [[RHS:s[0-9]+]]
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; GFX9: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
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; GFX9: v_pk_ashrrev_i16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
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define amdgpu_kernel void @ashr_v_s_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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%vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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%result = ashr <2 x i16> %vgpr, %sgpr
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store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}ashr_s_v_v2i16:
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; GFX9: s_load_dword [[LHS:s[0-9]+]]
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; GFX9: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
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; GFX9: v_pk_ashrrev_i16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
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define amdgpu_kernel void @ashr_s_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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%vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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%result = ashr <2 x i16> %sgpr, %vgpr
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store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}ashr_imm_v_v2i16:
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; GCN: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
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; GFX9: v_pk_ashrrev_i16 [[RESULT:v[0-9]+]], [[RHS]], -4
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define amdgpu_kernel void @ashr_imm_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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%vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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%result = ashr <2 x i16> <i16 -4, i16 -4>, %vgpr
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store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}ashr_v_imm_v2i16:
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; GCN: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
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; GFX9: v_pk_ashrrev_i16 [[RESULT:v[0-9]+]], 8, [[LHS]]
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define amdgpu_kernel void @ashr_v_imm_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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%out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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%vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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%result = ashr <2 x i16> %vgpr, <i16 8, i16 8>
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store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_ashr_v4i16:
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; GCN: {{buffer|flat|global}}_load_dwordx2
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; GCN: {{buffer|flat|global}}_load_dwordx2
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; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_ashrrev_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI: v_ashrrev_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_ashrrev_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: {{buffer|flat|global}}_store_dwordx2
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define amdgpu_kernel void @v_ashr_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
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%out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
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%b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in.gep, i32 1
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%a = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
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%b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr
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%result = ashr <4 x i16> %a, %b
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store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}ashr_v_imm_v4i16:
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; GCN: {{buffer|flat|global}}_load_dwordx2
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; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, 8, v{{[0-9]+}}
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; GFX9: v_pk_ashrrev_i16 v{{[0-9]+}}, 8, v{{[0-9]+}}
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; GCN: {{buffer|flat|global}}_store_dwordx2
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define amdgpu_kernel void @ashr_v_imm_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
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%out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
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%vgpr = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
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%result = ashr <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8>
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store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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