109 lines
5.0 KiB
LLVM
109 lines
5.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -stop-after=irtranslator -global-isel %s -o - | FileCheck %s
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; Check that we correctly skip over disabled inputs
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define amdgpu_ps void @disabled_input(float inreg %arg0, float %psinput0, float %psinput1) #1 {
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; CHECK-LABEL: name: disabled_input
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; CHECK: bb.1.main_body:
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; CHECK: liveins: $sgpr2, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY1]](s32), 0, 0
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; CHECK: S_ENDPGM 0
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main_body:
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg0, float %arg0, float %arg0, float %psinput1, i1 false, i1 false) #0
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ret void
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}
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define amdgpu_ps void @disabled_input_struct(float inreg %arg0, { float, float } %psinput0, float %psinput1) #1 {
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; CHECK-LABEL: name: disabled_input_struct
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; CHECK: bb.1.main_body:
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; CHECK: liveins: $sgpr2, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY1]](s32), 0, 0
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; CHECK: S_ENDPGM 0
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main_body:
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg0, float %arg0, float %arg0, float %psinput1, i1 false, i1 false) #0
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ret void
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}
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define amdgpu_ps float @vgpr_return(i32 %vgpr) {
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; CHECK-LABEL: name: vgpr_return
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: $vgpr0 = COPY [[COPY]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
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%cast = bitcast i32 %vgpr to float
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ret float %cast
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}
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define amdgpu_ps i32 @sgpr_return_i32(i32 %vgpr) {
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; CHECK-LABEL: name: sgpr_return_i32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32)
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; CHECK: $sgpr0 = COPY [[INT]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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ret i32 %vgpr
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}
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define amdgpu_ps i64 @sgpr_return_i64(i64 %vgpr) {
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; CHECK-LABEL: name: sgpr_return_i64
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
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; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)
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; CHECK: $sgpr0 = COPY [[INT]](s32)
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; CHECK: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)
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; CHECK: $sgpr1 = COPY [[INT1]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
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ret i64 %vgpr
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}
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define amdgpu_ps <2 x i32> @sgpr_return_v2i32(<2 x i32> %vgpr) {
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; CHECK-LABEL: name: sgpr_return_v2i32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)
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; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)
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; CHECK: $sgpr0 = COPY [[INT]](s32)
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; CHECK: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)
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; CHECK: $sgpr1 = COPY [[INT1]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
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ret <2 x i32> %vgpr
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}
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define amdgpu_ps { i32, i32 } @sgpr_struct_return_i32_i32(i32 %vgpr0, i32 %vgpr1) {
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; CHECK-LABEL: name: sgpr_struct_return_i32_i32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32)
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; CHECK: $sgpr0 = COPY [[INT]](s32)
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; CHECK: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
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; CHECK: $sgpr1 = COPY [[INT1]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
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%insertvalue0 = insertvalue { i32, i32 } undef, i32 %vgpr0, 0
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%value = insertvalue { i32, i32 } %insertvalue0, i32 %vgpr1, 1
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ret { i32, i32 } %value
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}
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declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #0
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attributes #0 = { nounwind }
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attributes #1 = { "InitialPSInputAddr"="0x00002" }
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