303 lines
8.9 KiB
Plaintext
303 lines
8.9 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
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---
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name: fabs_s32_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fabs_s32_ss
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
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; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_FABS %0
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$sgpr0 = COPY %1
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...
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---
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name: fabs_s32_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fabs_s32_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
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; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_FABS %0
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$vgpr0 = COPY %1
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...
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---
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name: fabs_s32_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fabs_s32_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
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; GCN: $vgpr0 = COPY [[FABS]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_FABS %0
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$vgpr0 = COPY %1
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...
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---
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name: fabs_v2s16_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: fabs_v2s16_ss
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
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; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_AND_B32_]]
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%0:sgpr(<2 x s16>) = COPY $sgpr0
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%1:sgpr(<2 x s16>) = G_FABS %0
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$sgpr0 = COPY %1
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...
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---
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name: fabs_s16_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fabs_s16_ss
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
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; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s16) = G_FABS %1
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%3:sgpr(s32) = G_ANYEXT %2
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$sgpr0 = COPY %3
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...
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---
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name: fabs_s16_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fabs_s16_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
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; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s16) = G_FABS %1
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%3:vgpr(s32) = G_ANYEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: fabs_s16_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fabs_s16_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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; GCN: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
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; GCN: $vgpr0 = COPY [[COPY1]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:vgpr(s16) = G_FABS %1
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%3:vgpr(s32) = G_ANYEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: fabs_v2s16_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: fabs_v2s16_vv
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; GCN: liveins: $vgpr0
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
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; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(<2 x s16>) = G_FABS %0
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$vgpr0 = COPY %1
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...
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---
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name: fabs_v2s16_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: fabs_v2s16_vs
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; GCN: liveins: $sgpr0
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; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
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; GCN: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
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; GCN: $vgpr0 = COPY [[FABS]](<2 x s16>)
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%0:sgpr(<2 x s16>) = COPY $sgpr0
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%1:vgpr(<2 x s16>) = G_FABS %0
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$vgpr0 = COPY %1
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...
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---
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name: fabs_s64_ss
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: fabs_s64_ss
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
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; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
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; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_FABS %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: fabs_s64_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: fabs_s64_vv
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
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; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s64) = G_FABS %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: fabs_s64_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: fabs_s64_vs
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
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; GCN: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
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; GCN: S_ENDPGM 0, implicit [[FABS]](s64)
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s64) = G_FABS %0
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S_ENDPGM 0, implicit %1
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...
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# Make sure the source register is constrained
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---
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name: fabs_s64_vv_no_src_constraint
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: fabs_s64_vv_no_src_constraint
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
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; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s64) = IMPLICIT_DEF
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%1:vgpr(s64) = G_FABS %0:vgpr(s64)
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S_ENDPGM 0, implicit %1
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...
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---
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name: fabs_s64_ss_no_src_constraint
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; GCN-LABEL: name: fabs_s64_ss_no_src_constraint
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; GCN: liveins: $sgpr0_sgpr1
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; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
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; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
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; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s64) = IMPLICIT_DEF
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%1:sgpr(s64) = G_FABS %0:sgpr(s64)
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S_ENDPGM 0, implicit %1
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...
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