701 lines
22 KiB
Plaintext
701 lines
22 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
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---
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name: test_build_vector_trunc_s_v2s16_s_s32_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_s32
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_trunc_s_pack_lh
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[COPY]], [[COPY1]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_CONSTANT i32 16
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%3:sgpr(s32) = G_LSHR %1, %2
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%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3
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S_ENDPGM 0, implicit %4
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...
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# There is no s_pack_hl_b32
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---
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name: test_build_vector_trunc_s_pack_lh_swapped
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_swapped
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
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; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[COPY]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_CONSTANT i32 16
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%3:sgpr(s32) = G_LSHR %1, %2
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%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0
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S_ENDPGM 0, implicit %4
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...
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---
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name: test_build_vector_trunc_s_pack_hh
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh
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; GFX9: liveins: $sgpr0, $sgpr1
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_PACK_HH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HH_B32_B16 [[COPY]], [[COPY1]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_CONSTANT i32 16
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%3:sgpr(s32) = G_LSHR %0, %2
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%4:sgpr(s32) = G_LSHR %1, %2
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%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
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S_ENDPGM 0, implicit %5
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...
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# TODO: Should this use an and instead?
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---
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name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_CONSTANT i32 0
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_CONSTANT i32 0
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: S_ENDPGM 0, implicit [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_IMPLICIT_DEF
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_IMPLICIT_DEF
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_trunc_s_v2s16_s_undef_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr1
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; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s_s32
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; GFX9: liveins: $sgpr1
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; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = G_IMPLICIT_DEF
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_trunc_s_v2s16_s_s32_undef
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_undef
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: S_ENDPGM 0, implicit [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_IMPLICIT_DEF
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_trunc_s_v2s16_s_zero_s_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr1
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; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_zero_s_s32
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; GFX9: liveins: $sgpr1
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; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = G_CONSTANT i32 0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_trunc_s_v2s16_s_s32_zero
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_zero
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
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; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_CONSTANT i32 0
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: test_build_vector_trunc_lshr16_zero
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GFX9-LABEL: name: test_build_vector_trunc_lshr16_zero
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; GFX9: liveins: $sgpr0
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; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], 16, implicit-def $scc
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; GFX9: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
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%0:sgpr(s32) = G_CONSTANT i32 0
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%1:sgpr(s32) = COPY $sgpr0
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%2:sgpr(s32) = G_CONSTANT i32 16
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%3:sgpr(s32) = G_LSHR %1, %2
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%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0
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S_ENDPGM 0, implicit %4
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...
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||
|
|
# Don't use pack since it would duplicate the shift use
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_pack_lh_multi_use
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $sgpr1
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_multi_use
|
||
|
|
; GFX9: liveins: $sgpr0, $sgpr1
|
||
|
|
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
|
||
|
|
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s32) = COPY $sgpr1
|
||
|
|
%2:sgpr(s32) = G_CONSTANT i32 16
|
||
|
|
%3:sgpr(s32) = G_LSHR %1, %2
|
||
|
|
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3
|
||
|
|
S_ENDPGM 0, implicit %4, implicit %3
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_pack_hh_multi_use_lhs
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $sgpr1
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_lhs
|
||
|
|
; GFX9: liveins: $sgpr0, $sgpr1
|
||
|
|
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
|
||
|
|
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
|
||
|
|
; GFX9: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[S_LSHR_B32_]], [[COPY1]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]], implicit [[S_LSHR_B32_]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s32) = COPY $sgpr1
|
||
|
|
%2:sgpr(s32) = G_CONSTANT i32 16
|
||
|
|
%3:sgpr(s32) = G_LSHR %0, %2
|
||
|
|
%4:sgpr(s32) = G_LSHR %1, %2
|
||
|
|
%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
|
||
|
|
S_ENDPGM 0, implicit %5, implicit %3
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_pack_hh_multi_use_rhs
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $sgpr1
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_rhs
|
||
|
|
; GFX9: liveins: $sgpr0, $sgpr1
|
||
|
|
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
|
||
|
|
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
|
||
|
|
; GFX9: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_1]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s32) = COPY $sgpr1
|
||
|
|
%2:sgpr(s32) = G_CONSTANT i32 16
|
||
|
|
%3:sgpr(s32) = G_LSHR %0, %2
|
||
|
|
%4:sgpr(s32) = G_LSHR %1, %2
|
||
|
|
%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
|
||
|
|
S_ENDPGM 0, implicit %5, implicit %4
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $sgpr1
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt
|
||
|
|
; GFX9: liveins: $sgpr0, $sgpr1
|
||
|
|
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
|
||
|
|
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s32) = COPY $sgpr1
|
||
|
|
%2:sgpr(s32) = G_CONSTANT i32 15
|
||
|
|
%3:sgpr(s32) = G_LSHR %1, %2
|
||
|
|
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3
|
||
|
|
S_ENDPGM 0, implicit %4
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0, $sgpr1
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt
|
||
|
|
; GFX9: liveins: $sgpr0, $sgpr1
|
||
|
|
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
|
||
|
|
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
|
||
|
|
; GFX9: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s32) = COPY $sgpr1
|
||
|
|
%2:sgpr(s32) = G_CONSTANT i32 15
|
||
|
|
%3:sgpr(s32) = G_LSHR %0, %2
|
||
|
|
%4:sgpr(s32) = G_LSHR %1, %2
|
||
|
|
%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
|
||
|
|
S_ENDPGM 0, implicit %5
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_constant_constant
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_constant
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]]
|
||
|
|
%0:sgpr(s32) = G_CONSTANT i32 123
|
||
|
|
%1:sgpr(s32) = G_CONSTANT i32 456
|
||
|
|
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_constant_impdef
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_impdef
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]]
|
||
|
|
%0:sgpr(s32) = G_CONSTANT i32 123
|
||
|
|
%1:sgpr(s32) = G_IMPLICIT_DEF
|
||
|
|
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_impdef_constant
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_constant
|
||
|
|
; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||
|
|
%0:sgpr(s32) = G_IMPLICIT_DEF
|
||
|
|
%1:sgpr(s32) = G_CONSTANT i32 123
|
||
|
|
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_impdef_impdef
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_impdef
|
||
|
|
; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[DEF]]
|
||
|
|
%0:sgpr(s32) = G_IMPLICIT_DEF
|
||
|
|
%1:sgpr(s32) = G_IMPLICIT_DEF
|
||
|
|
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]]
|
||
|
|
%0:sgpr(s16) = G_CONSTANT i16 123
|
||
|
|
%1:sgpr(s16) = G_CONSTANT i16 456
|
||
|
|
%2:sgpr(s32) = G_ZEXT %0
|
||
|
|
%3:sgpr(s32) = G_ZEXT %1
|
||
|
|
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
|
||
|
|
S_ENDPGM 0, implicit %4
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant
|
||
|
|
; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
|
||
|
|
; GFX9: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[DEF]], 1048576, implicit-def $scc
|
||
|
|
; GFX9: [[S_BFE_U32_1:%[0-9]+]]:sreg_32 = S_BFE_U32 [[S_MOV_B32_]], 1048576, implicit-def $scc
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_BFE_U32_]], [[S_BFE_U32_1]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||
|
|
%0:sgpr(s16) = G_IMPLICIT_DEF
|
||
|
|
%1:sgpr(s16) = G_CONSTANT i16 123
|
||
|
|
%2:sgpr(s32) = G_ZEXT %0
|
||
|
|
%3:sgpr(s32) = G_ZEXT %1
|
||
|
|
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
|
||
|
|
S_ENDPGM 0, implicit %4
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294836208
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]]
|
||
|
|
%0:sgpr(s16) = G_CONSTANT i16 -16
|
||
|
|
%1:sgpr(s16) = G_CONSTANT i16 -3
|
||
|
|
%2:sgpr(s32) = G_SEXT %0
|
||
|
|
%3:sgpr(s32) = G_SEXT %1
|
||
|
|
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
|
||
|
|
S_ENDPGM 0, implicit %4
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539
|
||
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|
; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]]
|
||
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%0:sgpr(s16) = G_CONSTANT i16 123
|
||
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|
%1:sgpr(s16) = G_CONSTANT i16 456
|
||
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|
%2:sgpr(s32) = G_ANYEXT %0
|
||
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%3:sgpr(s32) = G_ANYEXT %1
|
||
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|
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
|
||
|
|
S_ENDPGM 0, implicit %4
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant
|
||
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|
legalized: true
|
||
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|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant
|
||
|
|
; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||
|
|
%0:sgpr(s16) = G_IMPLICIT_DEF
|
||
|
|
%1:sgpr(s16) = G_CONSTANT i16 123
|
||
|
|
%2:sgpr(s32) = G_ANYEXT %0
|
||
|
|
%3:sgpr(s32) = G_ANYEXT %1
|
||
|
|
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3
|
||
|
|
S_ENDPGM 0, implicit %4
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_var_constant
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_var_constant
|
||
|
|
; GFX9: liveins: $sgpr0
|
||
|
|
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s32) = G_CONSTANT i32 456
|
||
|
|
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_constant_var
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_var
|
||
|
|
; GFX9: liveins: $sgpr0
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456
|
||
|
|
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||
|
|
%0:sgpr(s32) = G_CONSTANT i32 456
|
||
|
|
%1:sgpr(s32) = COPY $sgpr0
|
||
|
|
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_var_0
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_var_0
|
||
|
|
; GFX9: liveins: $sgpr0
|
||
|
|
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||
|
|
%0:sgpr(s32) = COPY $sgpr0
|
||
|
|
%1:sgpr(s32) = G_CONSTANT i32 0
|
||
|
|
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: test_build_vector_trunc_s_v2s16_0_var
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
tracksRegLiveness: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0
|
||
|
|
|
||
|
|
; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_0_var
|
||
|
|
; GFX9: liveins: $sgpr0
|
||
|
|
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||
|
|
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||
|
|
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
|
||
|
|
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||
|
|
%0:sgpr(s32) = G_CONSTANT i32 0
|
||
|
|
%1:sgpr(s32) = COPY $sgpr0
|
||
|
|
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|