116 lines
4.0 KiB
LLVM
116 lines
4.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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define <4 x i1> @t32_3(<4 x i32> %X) nounwind {
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; CHECK-LABEL: t32_3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: adrp x9, .LCPI0_1
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI0_1]
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 3, i32 3, i32 3, i32 3>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 2>
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ret <4 x i1> %cmp
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}
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define <4 x i1> @t32_5(<4 x i32> %X) nounwind {
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; CHECK-LABEL: t32_5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: mov w8, #52429
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; CHECK-NEXT: movk w8, #52428, lsl #16
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; CHECK-NEXT: mov w9, #13106
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; CHECK-NEXT: movk w9, #13107, lsl #16
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; CHECK-NEXT: dup v2.4s, w8
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; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: dup v1.4s, w9
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; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 5, i32 5>
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%cmp = icmp eq <4 x i32> %urem, <i32 1, i32 2, i32 3, i32 4>
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ret <4 x i1> %cmp
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}
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define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {
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; CHECK-LABEL: t32_6_part0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: adrp x9, .LCPI2_0
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI2_0]
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; CHECK-NEXT: umull2 v3.2d, v0.4s, v1.4s
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; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s
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; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: ushr v1.4s, v1.4s, #2
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; CHECK-NEXT: movi v3.4s, #6
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; CHECK-NEXT: mls v0.4s, v1.4s, v3.4s
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; CHECK-NEXT: cmeq v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i1> %cmp
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}
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define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind {
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; CHECK-LABEL: t32_6_part1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: adrp x9, .LCPI3_0
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI3_0]
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; CHECK-NEXT: umull2 v3.2d, v0.4s, v1.4s
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; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s
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; CHECK-NEXT: uzp2 v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: ushr v1.4s, v1.4s, #2
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; CHECK-NEXT: movi v3.4s, #6
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; CHECK-NEXT: mls v0.4s, v1.4s, v3.4s
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; CHECK-NEXT: cmeq v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>
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%cmp = icmp eq <4 x i32> %urem, <i32 4, i32 5, i32 0, i32 0>
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ret <4 x i1> %cmp
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}
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define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {
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; CHECK-LABEL: t32_tautological:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI4_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
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; CHECK-NEXT: adrp x8, .LCPI4_1
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_1]
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; CHECK-NEXT: adrp x8, .LCPI4_2
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI4_2]
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; CHECK-NEXT: adrp x8, .LCPI4_3
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; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI4_3]
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; CHECK-NEXT: adrp x8, .LCPI4_4
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; CHECK-NEXT: umull2 v5.2d, v0.4s, v1.4s
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; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s
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; CHECK-NEXT: neg v2.4s, v2.4s
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; CHECK-NEXT: uzp2 v1.4s, v1.4s, v5.4s
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; CHECK-NEXT: ldr q5, [x8, :lo12:.LCPI4_4]
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; CHECK-NEXT: ushl v1.4s, v1.4s, v2.4s
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; CHECK-NEXT: bit v1.16b, v0.16b, v3.16b
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; CHECK-NEXT: mls v0.4s, v1.4s, v4.4s
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; CHECK-NEXT: cmeq v0.4s, v0.4s, v5.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 1, i32 1, i32 2, i32 3>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 2>
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ret <4 x i1> %cmp
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}
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